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([50.120.71.169]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c7a2ae3f36sm1608755a91.13.2024.06.18.19.17.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jun 2024 19:17:25 -0700 (PDT) From: Doug Brown To: stable@vger.kernel.org Cc: Doug Brown , stable , Greg Kroah-Hartman Subject: [PATCH 5.10.y] serial: 8250_pxa: Configure tx_loadsz to match FIFO IRQ level Date: Tue, 18 Jun 2024 19:17:02 -0700 Message-Id: <20240619021701.503264-1-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <2024061757-squid-skating-bd26@gregkh> References: <2024061757-squid-skating-bd26@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The FIFO is 64 bytes, but the FCR is configured to fire the TX interrupt when the FIFO is half empty (bit 3 = 0). Thus, we should only write 32 bytes when a TX interrupt occurs. This fixes a problem observed on the PXA168 that dropped a bunch of TX bytes during large transmissions. Fixes: ab28f51c77cd ("serial: rewrite pxa2xx-uart to use 8250_core") Signed-off-by: Doug Brown Link: https://lore.kernel.org/r/20240519191929.122202-1-doug@schmorgal.com Cc: stable Signed-off-by: Greg Kroah-Hartman (cherry picked from commit 5208e7ced520a813b4f4774451fbac4e517e78b2) Signed-off-by: Doug Brown --- drivers/tty/serial/8250/8250_pxa.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tty/serial/8250/8250_pxa.c b/drivers/tty/serial/8250/8250_pxa.c index 33ca98bfa5b3..0780f5d7be62 100644 --- a/drivers/tty/serial/8250/8250_pxa.c +++ b/drivers/tty/serial/8250/8250_pxa.c @@ -125,6 +125,7 @@ static int serial_pxa_probe(struct platform_device *pdev) uart.port.regshift = 2; uart.port.irq = irq; uart.port.fifosize = 64; + uart.tx_loadsz = 32; uart.port.flags = UPF_IOREMAP | UPF_SKIP_TEST | UPF_FIXED_TYPE; uart.port.dev = &pdev->dev; uart.port.uartclk = clk_get_rate(data->clk); -- 2.34.1