From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5416B131BAF; Thu, 1 Aug 2024 00:28:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722472107; cv=none; b=i0FwRDHwMrtp5w0jO7KDtVpN4cs6JAGOlEou4KaI/GGrj652EECsqEGQe46b0Gja0V2VVbA5CZwRtquJr/zD7Crq6DMQFtU9Ce1TOe/ILJGSECxfLNunxl5uhHNCJRZm4xmG5D/hx+WIW2MQW+WEZbZtLgDQt/8VoBXWkSjQPYs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722472107; c=relaxed/simple; bh=OjoGGK4pUIVybToCjKqlarlVa8jvzJO0umWEbu4Oz7g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LyakxXwyY0v2g8fA1NNG9D6C48Z0Q82xkHyIjQCDq1ktNwDGPt+p++qiI0CXsftOG4FRqpTPDMWC2w9CRMha7ksfNtGdT9imdVeQ85YbXn6GZLlu/HI8VsHpYBxYIVFION1qa+W99fUJPawSlAadUWRanT5D/V4/0geZ4mIP0OA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IsHdWOyo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IsHdWOyo" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6CC53C116B1; Thu, 1 Aug 2024 00:28:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722472106; bh=OjoGGK4pUIVybToCjKqlarlVa8jvzJO0umWEbu4Oz7g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IsHdWOyomxvWwbgUBqD1gZMeM7QMqyk0EoCjcrf9DlCDQnuttcQbJm3sDvr/3kJCo B80ASI5JHfZPPutLdO9nj/Iof5yAAcyU+jKbr2dvW8wTmpBu6YCOm2viWafEGSSWyc ZmvrgMdhtGLeuclUtTRsa/6pt0DUHiACAOZelQXAZNjENaKZ3fd1GqVl6AGCXL9A6u I5Z06x9tLMB8M6z2xlDqPoVuwxm1M20ls7sxFGfyy24Z747mcyTHN26WaQmxWNWrsr DT+iC5qRQMmMcNR0sNntyvLhUEaReL04c10hINq3DFvFKYjWM0qtXDjwS/+JewbQac /G9b//iS4QxWg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Jesse Zhang , Jesse Zhang , Tim Huang , Alex Deucher , Sasha Levin , kenneth.feng@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch, Jun.Ma2@amd.com, mario.limonciello@amd.com, yifan1.zhang@amd.com, lijo.lazar@amd.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 6.1 05/61] drm/amd/pm: Fix negative array index read Date: Wed, 31 Jul 2024 20:25:23 -0400 Message-ID: <20240801002803.3935985-5-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240801002803.3935985-1-sashal@kernel.org> References: <20240801002803.3935985-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.1.102 Content-Transfer-Encoding: 8bit From: Jesse Zhang [ Upstream commit c8c19ebf7c0b202a6a2d37a52ca112432723db5f ] Avoid using the negative values for clk_idex as an index into an array pptable->DpmDescriptor. V2: fix clk_index return check (Tim Huang) Signed-off-by: Jesse Zhang Reviewed-by: Tim Huang Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 27 ++++++++++++++----- 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index ed2112efc6c68..286f4f9bfa352 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -1215,19 +1215,22 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, value); } -static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) +static int navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) { PPTable_t *pptable = smu->smu_table.driver_pptable; DpmDescriptor_t *dpm_desc = NULL; - uint32_t clk_index = 0; + int clk_index = 0; clk_index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_CLK, clk_type); + if (clk_index < 0) + return clk_index; + dpm_desc = &pptable->DpmDescriptor[clk_index]; /* 0 - Fine grained DPM, 1 - Discrete DPM */ - return dpm_desc->SnapToDiscrete == 0; + return dpm_desc->SnapToDiscrete == 0 ? 1 : 0; } static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap) @@ -1283,7 +1286,11 @@ static int navi10_emit_clk_levels(struct smu_context *smu, if (ret) return ret; - if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { + ret = navi10_is_support_fine_grained_dpm(smu, clk_type); + if (ret < 0) + return ret; + + if (!ret) { for (i = 0; i < count; i++) { ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); @@ -1492,7 +1499,11 @@ static int navi10_print_clk_levels(struct smu_context *smu, if (ret) return size; - if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { + ret = navi10_is_support_fine_grained_dpm(smu, clk_type); + if (ret < 0) + return ret; + + if (!ret) { for (i = 0; i < count; i++) { ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); if (ret) @@ -1661,7 +1672,11 @@ static int navi10_force_clk_levels(struct smu_context *smu, case SMU_UCLK: case SMU_FCLK: /* There is only 2 levels for fine grained DPM */ - if (navi10_is_support_fine_grained_dpm(smu, clk_type)) { + ret = navi10_is_support_fine_grained_dpm(smu, clk_type); + if (ret < 0) + return ret; + + if (ret) { soft_max_level = (soft_max_level >= 1 ? 1 : 0); soft_min_level = (soft_min_level >= 1 ? 1 : 0); } -- 2.43.0