From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03E6A53370 for ; Mon, 12 Aug 2024 14:51:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723474318; cv=none; b=ceJHxYyy1qP8DpeoIGWeOAlz+EfweD8jm3L7kdDfpPgumqvpLNLVhHbRSMmesYgozm9a8T9lBwq0+kU1Pf78DcRnhi+yyfwC2Ic2kPINggA0nReLVvh2S7y49HYS3Guvz2BuWW7ERJH6YyIroSebXv8DTu6WFWiXsm8hkPBEkKU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723474318; c=relaxed/simple; bh=QxiSNdf2x++cx6CZ2qIDVWwn3+QNzbGPZbun/NjZCgA=; h=Subject:To:Cc:From:Date:Message-ID:MIME-Version:Content-Type; b=HrUDrovK0v2Z+14N+VZO4uA8cQP7QzfzeQT9axQeld4sWY3DDFWbIimTujzrE9BELzPuKrI3qofFdgq1cAmfELnXbqgJ732B1z3h0tr8F10x5bQOjWSOByoviW8y5WW303vDywAfFV3cnVH6feRUDHCv2N+gk5bbVSHj4Y562SQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=SQFQLJoG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="SQFQLJoG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7D3C8C32782; Mon, 12 Aug 2024 14:51:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1723474317; bh=QxiSNdf2x++cx6CZ2qIDVWwn3+QNzbGPZbun/NjZCgA=; h=Subject:To:Cc:From:Date:From; b=SQFQLJoGmXA8HOZ9G/lIfkjlCfw2qRLuWUA/HaKTRBCZ6weYv5UTUMITIz3RZrSRH Yb9nPmAdx51zXOuAjnQjVoDvbwx2ZbNXQB9XUcdrdE8HtnagBAPooRZzK+7zC/YzM6 nv20ZqcapB9AqTSSksSXvtMin2E1DAkvf9dhYQ3A= Subject: FAILED: patch "[PATCH] drm/amd/display: Always enable HPO for DCN4 dGPU" failed to apply to 6.6-stable tree To: hanghong.ma@amd.com,alex.hung@amd.com,alexander.deucher@amd.com,daniel.wheeler@amd.com,mario.limonciello@amd.com,wenjing.liu@amd.com Cc: From: Date: Mon, 12 Aug 2024 16:49:49 +0200 Message-ID: <2024081249-hexagram-punctual-9262@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit The patch below does not apply to the 6.6-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.6.y git checkout FETCH_HEAD git cherry-pick -x a4758aa3d1d9ff1c7a05da58387d217c2cd0c38b # git commit -s git send-email --to '' --in-reply-to '2024081249-hexagram-punctual-9262@gregkh' --subject-prefix 'PATCH 6.6.y' HEAD^.. Possible dependencies: a4758aa3d1d9 ("drm/amd/display: Always enable HPO for DCN4 dGPU") 70839da63605 ("drm/amd/display: Add new DCN401 sources") thanks, greg k-h ------------------ original commit in Linus's tree ------------------ >From a4758aa3d1d9ff1c7a05da58387d217c2cd0c38b Mon Sep 17 00:00:00 2001 From: "Leo (Hanghong) Ma" Date: Tue, 11 Jun 2024 14:12:43 -0400 Subject: [PATCH] drm/amd/display: Always enable HPO for DCN4 dGPU [WHY && HOW] Some DP EDID CTS tests fail due to HPO disable, and we should keep it enable on DCN4 dGPU. Reviewed-by: Wenjing Liu Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Alex Hung Signed-off-by: Leo (Hanghong) Ma Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 42753f56d31d..79a911e1a09a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -408,6 +408,8 @@ void dcn401_init_hw(struct dc *dc) REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } + dcn401_setup_hpo_hw_control(hws, true); + if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c index 1cf0608e1980..8159fd838dc3 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c @@ -137,7 +137,6 @@ static const struct hwseq_private_funcs dcn401_private_funcs = { .program_mall_pipe_config = dcn32_program_mall_pipe_config, .update_force_pstate = dcn32_update_force_pstate, .update_mall_sel = dcn32_update_mall_sel, - .setup_hpo_hw_control = dcn401_setup_hpo_hw_control, .calculate_dccg_k1_k2_values = NULL, .apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw, .reset_back_end_for_pipe = dcn20_reset_back_end_for_pipe,