From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07BBA1714D0; Thu, 15 Aug 2024 13:36:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723729006; cv=none; b=q5ERaJ9nH/u1ObMowPTpCg9UOZBzDMRGuwV4jVp7ncXVNNiWICu4yW6SAimjl1Bwl8ibfFwW8w9m/hCVOdtFvFmuZMcxE1qqcn3+O9ke9cKIKptnEU2pLzAy34FznOBnMp8XtePmrYnk7cY10L52hxpNPPXUTN/69izuNccKceg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723729006; c=relaxed/simple; bh=oIMPwLHBTbMxIzvikKnM77IvS7EB4ARaGe7oJJHMUKc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DkyVycwC0TCl8v2NWHlNfoN8+ZIEiXwTyi8QAArn46oUuEIO25CwepnKJtrrZQVJ7+/8AmR9ed+VOGL6SF7EMzjxU1Fj2NBMsBNKy7w7V9vs9aqaSKWIrGXgS+67hRKSAQaLlsEuOmsE/KOnewVemUmpyt1X4yWJhOEfYJ33Eao= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=PH2LglGU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="PH2LglGU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7F748C4AF0A; Thu, 15 Aug 2024 13:36:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1723729005; bh=oIMPwLHBTbMxIzvikKnM77IvS7EB4ARaGe7oJJHMUKc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PH2LglGUK4236RhurZuSOA3RsShpwIxJUehODztbrDcasQFCdbesdjRVispZr+6sn gYPk8Ep47EcKnrdwVX6BVNJ13VzcUgo1bVDCTdXE7oPnXl7PQ5cP9eVUQuvFLWZzo2 amTsixrfE1fidqI80noDQdKiSm41h97jw9DOGkLQ= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Besar Wicaksono , James Clark , Will Deacon , Mark Rutland , Sasha Levin Subject: [PATCH 4.19 149/196] arm64: Add Neoverse-V2 part Date: Thu, 15 Aug 2024 15:24:26 +0200 Message-ID: <20240815131857.777506765@linuxfoundation.org> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240815131852.063866671@linuxfoundation.org> References: <20240815131852.063866671@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 4.19-stable review patch. If anyone has any objections, please let me know. ------------------ From: Besar Wicaksono [ Upstream commit f4d9d9dcc70b96b5e5d7801bd5fbf8491b07b13d ] Add the part number and MIDR for Neoverse-V2 Signed-off-by: Besar Wicaksono Reviewed-by: James Clark Link: https://lore.kernel.org/r/20240109192310.16234-2-bwicaksono@nvidia.com Signed-off-by: Will Deacon [ Mark: trivial backport ] Signed-off-by: Mark Rutland Signed-off-by: Sasha Levin --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 50368f9622139..0e4c0675f7461 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -89,6 +89,7 @@ #define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define ARM_CPU_PART_CORTEX_A78C 0xD4B +#define ARM_CPU_PART_NEOVERSE_V2 0xD4F #define APM_CPU_PART_POTENZA 0x000 @@ -125,6 +126,7 @@ #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) +#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) -- 2.43.0