From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C37D51DA4E; Thu, 15 Aug 2024 13:35:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723728937; cv=none; b=PPAukXEDrc3o9XuaTEz+2hwo0jGvaRqkU6DCA0wZLu7uK/X70gM27ItBOPgvnHIWratmH6DRh+OXe8Y7iy2zr5g3F64WwYiVXhmZXnm0j64ol+LE8ok81LczX5rMGGDFnykWJIdidrTXYaC6z2Pv/TO+wg7zCAb03MhvMM4/Dwk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723728937; c=relaxed/simple; bh=/Z7i05GdBvla17a2SK38mMdEQUdc0S4BL1CkMmxoRA4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jkGXQAV1RxAALDOse+nEuGWlt8Iz+HXYAbSgjxL7xZ/qx6ApVTllP1XZ1poSzo00zwddQshWbPx36OuHTgXWePq+NThTjczMqLXQJU/iPoUHiZZrLSXo50BtGixVRz7MfQ2wjpyMEBRGFmulVHZrBBFG8g1/nucsetbZS7rDQms= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=VgXNT5yN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="VgXNT5yN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4C7F3C4AF0C; Thu, 15 Aug 2024 13:35:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1723728937; bh=/Z7i05GdBvla17a2SK38mMdEQUdc0S4BL1CkMmxoRA4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VgXNT5yNiR4qM93Aelh/JTS+pSnnSuGZRUxtAGp3fF7fab/1GxbhQgT9hXhGB7Qww wPvzm4cQOyqJHOeAPjexfgOQxXdNOLuz7ubTCMuiNdnVYIJqDcsMLg7pHPQwADWPFW XzXq0QCWvKx5/p17ICFK/xt1MYBBBbGzn00HX6+o= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Mark Rutland , James Morse , Will Deacon , Anshuman Khandual , Catalin Marinas , Sasha Levin Subject: [PATCH 4.19 159/196] arm64: cputype: Add Cortex-A725 definitions Date: Thu, 15 Aug 2024 15:24:36 +0200 Message-ID: <20240815131858.158468690@linuxfoundation.org> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240815131852.063866671@linuxfoundation.org> References: <20240815131852.063866671@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 4.19-stable review patch. If anyone has any objections, please let me know. ------------------ From: Mark Rutland [ Upstream commit 9ef54a384526911095db465e77acc1cb5266b32c ] Add cputype definitions for Cortex-A725. These will be used for errata detection in subsequent patches. These values can be found in the Cortex-A725 TRM: https://developer.arm.com/documentation/107652/0001/ ... in table A-247 ("MIDR_EL1 bit descriptions"). Signed-off-by: Mark Rutland Cc: James Morse Cc: Will Deacon Reviewed-by: Anshuman Khandual Link: https://lore.kernel.org/r/20240801101803.1982459-3-mark.rutland@arm.com Signed-off-by: Catalin Marinas [ Mark: trivial backport ] Signed-off-by: Mark Rutland Signed-off-by: Sasha Levin --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index ad054869acf6b..f8be4d7ecde28 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -96,6 +96,7 @@ #define ARM_CPU_PART_CORTEX_X4 0xD82 #define ARM_CPU_PART_NEOVERSE_V3 0xD84 #define ARM_CPU_PART_CORTEX_X925 0xD85 +#define ARM_CPU_PART_CORTEX_A725 0xD87 #define APM_CPU_PART_POTENZA 0x000 @@ -139,6 +140,7 @@ #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925) +#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) -- 2.43.0