From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 640307DA7D; Thu, 15 Aug 2024 13:59:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730391; cv=none; b=N5M2cJ+yi7MJ9l5kIMrBeqblyPJXfbJuchaTM9Qf8oQF7keT5Pq4+nkqJ9bFpSRgA2ojAlslVVVuHvNDJkL4wupNnZ4eSMjQv1xHGoYZt2KbYM7Qer1iVfbQ5bM44DRH+0n3jmpKHdWmGPOKf5k74MLvyIlEK74IzKJx7s3Z2FI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723730391; c=relaxed/simple; bh=8mmk5G9aeEMzkc1pVMt0a4bATA4dQ1lZxW4Y147K/B8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XDrVEZwwXD+xV8MD4CpqtsNa6Vj2wgjpKX6iMG1VZf3/RzuUsCqbN/4FIR8oaetMAcFwQhhSZt7G5C2b5SBwFQRjgdXzFw+VT2uBp/BNJHqzHyiQnbfSJWxVMwebznZWIDBlJigQ4pvlEL2PVCIUxIVw+3mi8F+bx30GzRfJYhc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=P6K5y+NQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="P6K5y+NQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C707EC32786; Thu, 15 Aug 2024 13:59:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1723730391; bh=8mmk5G9aeEMzkc1pVMt0a4bATA4dQ1lZxW4Y147K/B8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P6K5y+NQKMPLpYb3/t3PbscJ21Ok49qFGMxUsX1ydP66BP0+fNGI1su+USaFE14mP oNjUwGXBwmfNlXfB4nZh4OSm5HTwkukpnsp5GOD16B0WfXMnV+yP/k7ywh9giUb7Sh s8yGbfYOxVJVEo7CeMQ4Euh2fZ/p9/WG0mXifwUg= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Besar Wicaksono , James Clark , Will Deacon , Mark Rutland , Sasha Levin Subject: [PATCH 5.15 393/484] arm64: Add Neoverse-V2 part Date: Thu, 15 Aug 2024 15:24:11 +0200 Message-ID: <20240815131956.626611936@linuxfoundation.org> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240815131941.255804951@linuxfoundation.org> References: <20240815131941.255804951@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.15-stable review patch. If anyone has any objections, please let me know. ------------------ From: Besar Wicaksono [ Upstream commit f4d9d9dcc70b96b5e5d7801bd5fbf8491b07b13d ] Add the part number and MIDR for Neoverse-V2 Signed-off-by: Besar Wicaksono Reviewed-by: James Clark Link: https://lore.kernel.org/r/20240109192310.16234-2-bwicaksono@nvidia.com Signed-off-by: Will Deacon [ Mark: trivial backport ] Signed-off-by: Mark Rutland Signed-off-by: Sasha Levin --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 3656bbbb7c7b6..d6d3f15c80aae 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -85,6 +85,7 @@ #define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define ARM_CPU_PART_CORTEX_A78C 0xD4B +#define ARM_CPU_PART_NEOVERSE_V2 0xD4F #define APM_CPU_PART_POTENZA 0x000 @@ -139,6 +140,7 @@ #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) +#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) -- 2.43.0