From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB56B18B491; Tue, 10 Sep 2024 10:02:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725962547; cv=none; b=TlVORlpEZQ7INZyqhmGVROd1KcEspXbj0+8hSpb3wFj1Fe7P3dskJKXN4fwS4fTH7yzdZJZcn4U8zE5xvT2gc5y6hwnA+BNMdRi8sANOPnJXGqq+pg5yFDK0fj/YyuBRWAgVm/g1pjeQpS1IwWeRCV1DaXCTt9vh1kpPoeiK2Yo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725962547; c=relaxed/simple; bh=NR5vkcZFMIWPj3Zeowq/7ykdEvbbD1+/B1wwl/AJfgY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ihIGnILzltWctcWsj/hlbls5fAnCGYA/UmiYtGt7ccrlKrMNT6BS2hvzeXNr7xQD6Iglsb82CWgd9CIQ3XRWGY1mxrW6eMi2EZsDLhYwU9WuGIef1SFzpMyI/Qb/Ay3PiNjAc0oa5IL9MQrjY5S3dAp9+CW5tYYxOdp3W248biU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=M9o9Tqqt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="M9o9Tqqt" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 70D71C4CEC3; Tue, 10 Sep 2024 10:02:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1725962546; bh=NR5vkcZFMIWPj3Zeowq/7ykdEvbbD1+/B1wwl/AJfgY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M9o9TqqtiVRBISvLSps76g3xhKyBHZBqEYMkYxNgvIluwoMQfKP/EkQMj9PxWRorE tjuwCqYrfPmuR9nqGLtYEGFSMZg5n6XDI0cKrDqSbsArwKBU9Meffm7BNpp1xst7k8 JMteyOQVPIFt4FB5lypoMOeAG5/wLXgvIkiA1XBs= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Jacob Pan , Kevin Tian , Yi Liu , Lu Baolu , Will Deacon , Sasha Levin Subject: [PATCH 5.4 071/121] iommu/vt-d: Handle volatile descriptor status read Date: Tue, 10 Sep 2024 11:32:26 +0200 Message-ID: <20240910092549.254966941@linuxfoundation.org> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240910092545.737864202@linuxfoundation.org> References: <20240910092545.737864202@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.4-stable review patch. If anyone has any objections, please let me know. ------------------ From: Jacob Pan [ Upstream commit b5e86a95541cea737394a1da967df4cd4d8f7182 ] Queued invalidation wait descriptor status is volatile in that IOMMU hardware writes the data upon completion. Use READ_ONCE() to prevent compiler optimizations which ensures memory reads every time. As a side effect, READ_ONCE() also enforces strict types and may add an extra instruction. But it should not have negative performance impact since we use cpu_relax anyway and the extra time(by adding an instruction) may allow IOMMU HW request cacheline ownership easier. e.g. gcc 12.3 BEFORE: 81 38 ad de 00 00 cmpl $0x2,(%rax) AFTER (with READ_ONCE()) 772f: 8b 00 mov (%rax),%eax 7731: 3d ad de 00 00 cmp $0x2,%eax //status data is 32 bit Signed-off-by: Jacob Pan Reviewed-by: Kevin Tian Reviewed-by: Yi Liu Link: https://lore.kernel.org/r/20240607173817.3914600-1-jacob.jun.pan@linux.intel.com Signed-off-by: Lu Baolu Link: https://lore.kernel.org/r/20240702130839.108139-2-baolu.lu@linux.intel.com Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- drivers/iommu/dmar.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c index 36900d65386f..a4805d17317d 100644 --- a/drivers/iommu/dmar.c +++ b/drivers/iommu/dmar.c @@ -1294,7 +1294,7 @@ int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu) */ writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG); - while (qi->desc_status[wait_index] != QI_DONE) { + while (READ_ONCE(qi->desc_status[wait_index]) != QI_DONE) { /* * We will leave the interrupts disabled, to prevent interrupt * context to queue another cmd while a cmd is already submitted -- 2.43.0