From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F283418C331; Tue, 10 Sep 2024 09:44:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725961447; cv=none; b=VEmRrZdNlMXqBb1QSrHI1sqXl9Qz+iBpjm9ybsICS3tEoaDBkWbuv5wAbpeIcNS9nCWfbuCpuJpJBUKuMabFpEbkHyDINiloUSyFwdLhkcOB8KH3RcbBbNJPZ4/MTln3j5I7rTnVYuTSIIab22qV16mUEK+kzQS5RwT0ftA8ijw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725961447; c=relaxed/simple; bh=2sABbx0E7nRqwP27xA79WNC0dK8CNYtDAN9XjgARU+Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WdV4ERFdhO1Cxu0N8CTX7KtscbHBVFQ3h/f9TkbSkYEPhWBUSzbWi81Hd9z88Lc+yTC7A9nK8Pt5ZEO6NgIefEnfENttpoWMN84b/mttkfCKn1c2SVbFFVludbEeIcOg6f759i4UE2OnFO4jClZZx1VQUuwAdTwaNbvMYikYoac= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=BWZ/epwN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="BWZ/epwN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7794AC4CEC3; Tue, 10 Sep 2024 09:44:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1725961446; bh=2sABbx0E7nRqwP27xA79WNC0dK8CNYtDAN9XjgARU+Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BWZ/epwNVwr7cjk2OnGadqPB0ab+W6c9EiQZIEU7m2C8CkfXYdITneAHN4RQmnZP/ aJBdSMMzIE4KnA5PSdI1dp+DFGuqNtTVdJc93ubDsjjeMgV0l3hAWbrvbXLYIlMLA4 AaZ1skVOVWEM1ANnkFkF81wIoRC4lpBMokRHrya0= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Emil Renner Berthing , Xingyu Wu , Hal Feng , Michael Jeanson , Stephen Boyd Subject: [PATCH 6.10 046/375] clk: starfive: jh7110-sys: Add notifier for PLL0 clock Date: Tue, 10 Sep 2024 11:27:23 +0200 Message-ID: <20240910092623.788530003@linuxfoundation.org> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240910092622.245959861@linuxfoundation.org> References: <20240910092622.245959861@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.10-stable review patch. If anyone has any objections, please let me know. ------------------ From: Xingyu Wu commit 538d5477b25289ac5d46ca37b9e5b4d685cbe019 upstream. Add notifier function for PLL0 clock. In the function, the cpu_root clock should be operated by saving its current parent and setting a new safe parent (osc clock) before setting the PLL0 clock rate. After setting PLL0 rate, it should be switched back to the original parent clock. Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC") Cc: stable@vger.kernel.org Reviewed-by: Emil Renner Berthing Signed-off-by: Xingyu Wu Link: https://lore.kernel.org/r/20240826080430.179788-2-xingyu.wu@starfivetech.com Reviewed-by: Hal Feng Tested-by: Michael Jeanson Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman --- drivers/clk/starfive/clk-starfive-jh7110-sys.c | 31 ++++++++++++++++++++++++- drivers/clk/starfive/clk-starfive-jh71x0.h | 2 + 2 files changed, 32 insertions(+), 1 deletion(-) --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c @@ -385,6 +385,32 @@ int jh7110_reset_controller_register(str } EXPORT_SYMBOL_GPL(jh7110_reset_controller_register); +/* + * This clock notifier is called when the rate of PLL0 clock is to be changed. + * The cpu_root clock should save the curent parent clock and switch its parent + * clock to osc before PLL0 rate will be changed. Then switch its parent clock + * back after the PLL0 rate is completed. + */ +static int jh7110_pll0_clk_notifier_cb(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct jh71x0_clk_priv *priv = container_of(nb, struct jh71x0_clk_priv, pll_clk_nb); + struct clk *cpu_root = priv->reg[JH7110_SYSCLK_CPU_ROOT].hw.clk; + int ret = 0; + + if (action == PRE_RATE_CHANGE) { + struct clk *osc = clk_get(priv->dev, "osc"); + + priv->original_clk = clk_get_parent(cpu_root); + ret = clk_set_parent(cpu_root, osc); + clk_put(osc); + } else if (action == POST_RATE_CHANGE) { + ret = clk_set_parent(cpu_root, priv->original_clk); + } + + return notifier_from_errno(ret); +} + static int __init jh7110_syscrg_probe(struct platform_device *pdev) { struct jh71x0_clk_priv *priv; @@ -413,7 +439,10 @@ static int __init jh7110_syscrg_probe(st if (IS_ERR(priv->pll[0])) return PTR_ERR(priv->pll[0]); } else { - clk_put(pllclk); + priv->pll_clk_nb.notifier_call = jh7110_pll0_clk_notifier_cb; + ret = clk_notifier_register(pllclk, &priv->pll_clk_nb); + if (ret) + return ret; priv->pll[0] = NULL; } --- a/drivers/clk/starfive/clk-starfive-jh71x0.h +++ b/drivers/clk/starfive/clk-starfive-jh71x0.h @@ -114,6 +114,8 @@ struct jh71x0_clk_priv { spinlock_t rmw_lock; struct device *dev; void __iomem *base; + struct clk *original_clk; + struct notifier_block pll_clk_nb; struct clk_hw *pll[3]; struct jh71x0_clk reg[]; };