From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6E3B13AD09; Tue, 10 Sep 2024 09:50:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725961834; cv=none; b=RtKWx7O2uvLIIlf1v97K3AIhPx8l8oPn4zIovR2Guikn4SIWnfo1rMG1rihNB50bc1RUitf9T4F5T8/zyr0vzGAPZA0b5f8774chPJ7lXJsaJ3tlTQ8x/1H/Zu+rOr7MNvKQiuca3tF8Z4skkau+Fx6WZCzU65mtg0LTv+sjK6I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725961834; c=relaxed/simple; bh=AwhZ8/pKCAKxpYxxMTQV2fJmuSm/yZj6pYU58zEhKDU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fSH3VCJCd16sfIK7kAvSZoypy2ypVYGA926xd8Za2JFAkjblf0b/9fzg5H287DmHH95qbcbQSe6oWlBFBY/K0MKhLLcdVdJpFBbovReO+tP92mXlCQMwbt4GrLrAylDaUbQEWQiSn5XDKku9632b6ZWnXX9r3G+kIAKZUemsVwc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=uRovMVNk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="uRovMVNk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 35919C4CEC3; Tue, 10 Sep 2024 09:50:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1725961834; bh=AwhZ8/pKCAKxpYxxMTQV2fJmuSm/yZj6pYU58zEhKDU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uRovMVNkxyoj+v1cTtd35c9hOkex+QKf3II0kPCM47UWUxBWpT6GQ35iCwE4pSAms NWY1pL1EocM7CFaX5KaY6Mr+hATJw0iXXUG+td7/soOQzzR6NvTdgAQKpX/h+waP09 ClmSA00DLIg2V2jKJ74C92hMvn5/IO6EF7DJMDRQ= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Jacob Pan , Kevin Tian , Yi Liu , Lu Baolu , Will Deacon , Sasha Levin Subject: [PATCH 6.10 205/375] iommu/vt-d: Handle volatile descriptor status read Date: Tue, 10 Sep 2024 11:30:02 +0200 Message-ID: <20240910092629.392788318@linuxfoundation.org> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240910092622.245959861@linuxfoundation.org> References: <20240910092622.245959861@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.10-stable review patch. If anyone has any objections, please let me know. ------------------ From: Jacob Pan [ Upstream commit b5e86a95541cea737394a1da967df4cd4d8f7182 ] Queued invalidation wait descriptor status is volatile in that IOMMU hardware writes the data upon completion. Use READ_ONCE() to prevent compiler optimizations which ensures memory reads every time. As a side effect, READ_ONCE() also enforces strict types and may add an extra instruction. But it should not have negative performance impact since we use cpu_relax anyway and the extra time(by adding an instruction) may allow IOMMU HW request cacheline ownership easier. e.g. gcc 12.3 BEFORE: 81 38 ad de 00 00 cmpl $0x2,(%rax) AFTER (with READ_ONCE()) 772f: 8b 00 mov (%rax),%eax 7731: 3d ad de 00 00 cmp $0x2,%eax //status data is 32 bit Signed-off-by: Jacob Pan Reviewed-by: Kevin Tian Reviewed-by: Yi Liu Link: https://lore.kernel.org/r/20240607173817.3914600-1-jacob.jun.pan@linux.intel.com Signed-off-by: Lu Baolu Link: https://lore.kernel.org/r/20240702130839.108139-2-baolu.lu@linux.intel.com Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- drivers/iommu/intel/dmar.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c index 304e84949ca7..1c8d3141cb55 100644 --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -1446,7 +1446,7 @@ int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc, */ writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG); - while (qi->desc_status[wait_index] != QI_DONE) { + while (READ_ONCE(qi->desc_status[wait_index]) != QI_DONE) { /* * We will leave the interrupts disabled, to prevent interrupt * context to queue another cmd while a cmd is already submitted -- 2.43.0