From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 664511B86F3; Wed, 25 Sep 2024 11:42:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727264563; cv=none; b=MfGx4hdX8o2vBM+pWKB57bMJB/kQ9yJmJp2drdBCDKeLb7FcZb2pzNLgiji3Idso/4gBmA8+9lY6i+DZZNPmZQMwf0Gv1s7c2kd85nScZsQ1IGDAzBmntf5uNnTcraVyUDj8XERVpTFd3uHO+9IHCvNORHEip5gf0U+IprWtV+Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727264563; c=relaxed/simple; bh=yzNlYsgajpQ/zA+oUraAwkJK47H9llH0Csgu5fvvEJ4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lObXgPgdr8qf0SRK0LejaBxmtLK+ZFQSZ577M0zj7jKIGO2EHwzZGI3iLueqtMQ7n9wi+a/Z3luHKCnRelWrsbIcu4KycuK5d6w1wt8epQ9/Tvi1cTFizG5K81sXMP45p3ls/KIU4VNds6p7uwdjp+lHquqeBybdDRlQ52X7hpE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oCqIUBFx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oCqIUBFx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id ABFB5C4CEC7; Wed, 25 Sep 2024 11:42:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727264563; bh=yzNlYsgajpQ/zA+oUraAwkJK47H9llH0Csgu5fvvEJ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oCqIUBFxYNM7zP8QB7WEI1gmqj7usBla2NiytDYI4VhNfkSSBbUfLYnU2mhjS9rf5 JP1gWywGM6Zfge7eYxv2l5020gLIDae+IPofkDDiW+F5gU8KSdYv/XpV1UfPpx9jty uZTc7yIhYV/d23RCVNYP3XL+4kb05J2sFa/wMHssklCR2AHXwZ6SxjUBiAZQrjGJWs pgZz33OJ4DSRX/86IuI3yKJV38BYSv9YazjZHqHDbYuN8fmyuf4CSIFI2WQhceDu4u TuT6q2Gvp+dn5Ie3ZuEcayyFfrxk+oBfpkGw47czPFRpEfQfHTRRfCte3U44aI4SnH bqnKr39HzkfXA== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Lu Baolu , Yi Liu , Joerg Roedel , Sasha Levin , dwmw2@infradead.org, joro@8bytes.org, will@kernel.org, iommu@lists.linux.dev Subject: [PATCH AUTOSEL 6.11 126/244] iommu/vt-d: Unconditionally flush device TLB for pasid table updates Date: Wed, 25 Sep 2024 07:25:47 -0400 Message-ID: <20240925113641.1297102-126-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240925113641.1297102-1-sashal@kernel.org> References: <20240925113641.1297102-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.11 Content-Transfer-Encoding: 8bit From: Lu Baolu [ Upstream commit 1f5e307ca16c0c19186cbd56ac460a687e6daba0 ] The caching mode of an IOMMU is irrelevant to the behavior of the device TLB. Previously, commit <304b3bde24b5> ("iommu/vt-d: Remove caching mode check before device TLB flush") removed this redundant check in the domain unmap path. Checking the caching mode before flushing the device TLB after a pasid table entry is updated is unnecessary and can lead to inconsistent behavior. Extends this consistency by removing the caching mode check in the pasid table update path. Suggested-by: Yi Liu Signed-off-by: Lu Baolu Link: https://lore.kernel.org/r/20240820030208.20020-1-baolu.lu@linux.intel.com Signed-off-by: Joerg Roedel Signed-off-by: Sasha Levin --- drivers/iommu/intel/pasid.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index b51fc268dc845..2e5fa0a232999 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -264,9 +264,7 @@ void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev, else iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); - /* Device IOTLB doesn't need to be flushed in caching mode. */ - if (!cap_caching_mode(iommu->cap)) - devtlb_invalidation_with_pasid(iommu, dev, pasid); + devtlb_invalidation_with_pasid(iommu, dev, pasid); } /* @@ -493,9 +491,7 @@ int intel_pasid_setup_dirty_tracking(struct intel_iommu *iommu, iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); - /* Device IOTLB doesn't need to be flushed in caching mode. */ - if (!cap_caching_mode(iommu->cap)) - devtlb_invalidation_with_pasid(iommu, dev, pasid); + devtlb_invalidation_with_pasid(iommu, dev, pasid); return 0; } @@ -572,9 +568,7 @@ void intel_pasid_setup_page_snoop_control(struct intel_iommu *iommu, pasid_cache_invalidation_with_pasid(iommu, did, pasid); qi_flush_piotlb(iommu, did, pasid, 0, -1, 0); - /* Device IOTLB doesn't need to be flushed in caching mode. */ - if (!cap_caching_mode(iommu->cap)) - devtlb_invalidation_with_pasid(iommu, dev, pasid); + devtlb_invalidation_with_pasid(iommu, dev, pasid); } /** -- 2.43.0