From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01AC439FD6; Mon, 21 Oct 2024 10:30:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729506638; cv=none; b=J/x6BQZziFxLaziB8EJ0fkj4G0C1gt3H2nVrViFCOoFRt2AIr/LAtHMqNY1Y+okQ3tukA7Mx8v7kE88Rm+p6ubIRmDMKBykMBQxZjvnm4lx5CrUkBlBfExGNtWA2dXUU5LpaBizhew+4KR0oRar860Qnjd0HOA/a86tZjnlNeRE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729506638; c=relaxed/simple; bh=vGsCdRARHjdF8aNC3HmOIje5mLYZ+ttR3Ag3KUd0ldA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=I9SHVXO5no5yhSQ0vmaDGEWnEi6bbYTP+6cGWmZETK0Q4FUSfqgOjwWmPmzhm0RzzFTHa4G662lk85HDndYUAQCQm+5mhHM9qu/3Mp963AeR7spZ052Sqblal6KrZ9Xgrm7ZDYZB4zBbNm03SvqLzrsS0rih2zHhvhfpZ1nt3dk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=OQV1Rnhq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="OQV1Rnhq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6B52EC4CEC3; Mon, 21 Oct 2024 10:30:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1729506637; bh=vGsCdRARHjdF8aNC3HmOIje5mLYZ+ttR3Ag3KUd0ldA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OQV1Rnhq25IP7PTxZ66lv3LNGfrLk7qhRBd18yjdcUG5LaNRM74nzMe9OWd75W/Ou JubOA1grqaPW3mpaoyZR3l/nZ+v2V1HTvApm1y+kDOP0U8X85K+ftuRgwSOKAo2apP OSGRL0tqaqGlgi7SN8llMFiVXI2hFXUKFQAWQ05E= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Venkatesh Srinivas , Jim Mattson , "Borislav Petkov (AMD)" , Tom Lendacky , Thomas Gleixner , stable@kernel.org Subject: [PATCH 6.11 041/135] x86/cpufeatures: Define X86_FEATURE_AMD_IBPB_RET Date: Mon, 21 Oct 2024 12:23:17 +0200 Message-ID: <20241021102300.939156892@linuxfoundation.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241021102259.324175287@linuxfoundation.org> References: <20241021102259.324175287@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.11-stable review patch. If anyone has any objections, please let me know. ------------------ From: Jim Mattson commit ff898623af2ed564300752bba83a680a1e4fec8d upstream. AMD's initial implementation of IBPB did not clear the return address predictor. Beginning with Zen4, AMD's IBPB *does* clear the return address predictor. This behavior is enumerated by CPUID.80000008H:EBX.IBPB_RET[30]. Define X86_FEATURE_AMD_IBPB_RET for use in KVM_GET_SUPPORTED_CPUID, when determining cross-vendor capabilities. Suggested-by: Venkatesh Srinivas Signed-off-by: Jim Mattson Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Tom Lendacky Reviewed-by: Thomas Gleixner Cc: Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/cpufeatures.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -215,7 +215,7 @@ #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* Disable Speculative Store Bypass. */ #define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* AMD SSBD implementation via LS_CFG MSR */ #define X86_FEATURE_IBRS ( 7*32+25) /* "ibrs" Indirect Branch Restricted Speculation */ -#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier */ +#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier without a guaranteed RSB flush */ #define X86_FEATURE_STIBP ( 7*32+27) /* "stibp" Single Thread Indirect Branch Predictors */ #define X86_FEATURE_ZEN ( 7*32+28) /* Generic flag for all Zen and newer */ #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* L1TF workaround PTE inversion */ @@ -348,6 +348,7 @@ #define X86_FEATURE_CPPC (13*32+27) /* "cppc" Collaborative Processor Performance Control */ #define X86_FEATURE_AMD_PSFD (13*32+28) /* Predictive Store Forwarding Disable */ #define X86_FEATURE_BTC_NO (13*32+29) /* Not vulnerable to Branch Type Confusion */ +#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* IBPB clears return address predictor */ #define X86_FEATURE_BRS (13*32+31) /* "brs" Branch Sampling available */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */