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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241127103016.3481128-9-cassel@kernel.org> On Wed, Nov 27, 2024 at 11:30:17AM +0100, Niklas Cassel wrote: > The DWC Databook description for the LWR_TARGET_RW and LWR_TARGET_HW fields > in the IATU_LWR_TARGET_ADDR_OFF_INBOUND_i registers state that: > "Field size depends on log2(BAR_MASK+1) in BAR match mode." > > I.e. only the upper bits are writable, and the number of writable bits is > dependent on the configured BAR_MASK. > > If we do not write the BAR_MASK before writing the iATU registers, we are > relying the reset value of the BAR_MASK being larger than the requested > size of the first set_bar() call. The reset value of the BAR_MASK is SoC > dependent. > > Thus, if the first set_bar() call requests a size that is larger than the > reset value of the BAR_MASK, the iATU will try to write to read-only bits, > which will cause the iATU to end up redirecting to a physical address that > is different from the address that was intended. > > Thus, we should always write the iATU registers after writing the BAR_MASK. > > Cc: stable@vger.kernel.org > Fixes: f8aed6ec624f ("PCI: dwc: designware: Add EP mode support") > Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam - Mani > --- > .../pci/controller/dwc/pcie-designware-ep.c | 28 ++++++++++--------- > 1 file changed, 15 insertions(+), 13 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > index f3ac7d46a855..bad588ef69a4 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > @@ -222,19 +222,10 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, > if ((flags & PCI_BASE_ADDRESS_MEM_TYPE_64) && (bar & 1)) > return -EINVAL; > > - reg = PCI_BASE_ADDRESS_0 + (4 * bar); > - > - if (!(flags & PCI_BASE_ADDRESS_SPACE)) > - type = PCIE_ATU_TYPE_MEM; > - else > - type = PCIE_ATU_TYPE_IO; > - > - ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar); > - if (ret) > - return ret; > - > if (ep->epf_bar[bar]) > - return 0; > + goto config_atu; > + > + reg = PCI_BASE_ADDRESS_0 + (4 * bar); > > dw_pcie_dbi_ro_wr_en(pci); > > @@ -246,9 +237,20 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, > dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0); > } > > - ep->epf_bar[bar] = epf_bar; > dw_pcie_dbi_ro_wr_dis(pci); > > +config_atu: > + if (!(flags & PCI_BASE_ADDRESS_SPACE)) > + type = PCIE_ATU_TYPE_MEM; > + else > + type = PCIE_ATU_TYPE_IO; > + > + ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar); > + if (ret) > + return ret; > + > + ep->epf_bar[bar] = epf_bar; > + > return 0; > } > > -- > 2.47.0 > -- மணிவண்ணன் சதாசிவம்