From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AC751527AC; Fri, 6 Dec 2024 15:13:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733498013; cv=none; b=RYopyi0EJQZn1wkk5uQbtJV2lsF1Ptww35NHx6pITpCAttlf4kIKIiCHAywExH+CYstT3rbfVhb/+Bm+a5xtRM8YNcYHbtbM48NZX+3SrNF/m4VEsrgI0M0WdDuXm2W34K7uwcGPXij9n0tjgieKpDcXmrGkT7NNeirSRTDu/34= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733498013; c=relaxed/simple; bh=eDsa+bDEfbsQ12xPcUwH0Nh1J2AyNt4VXb9QeS1lep0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HOYQ1w1NSbc7RdOgrmI1x448Bhk8xQBbxxl8X5O3SbGazNwG5+b6q29SEVqCP3SIDlIPuFmfFj6hOiYiEozPk8XNKcyySQlAdr+4bxwStrD5plaQrKe22V+0GAm16iyv/Kd3LRPLh09L3nUGZIjymNWtlKTjGLA9jep1UOpWF64= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=CxXn8mcx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="CxXn8mcx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8F09AC4CED1; Fri, 6 Dec 2024 15:13:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1733498013; bh=eDsa+bDEfbsQ12xPcUwH0Nh1J2AyNt4VXb9QeS1lep0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CxXn8mcxdCU1N2NzFb/U+MWDxtl066UeCNT1AD+tZS/mvBLzXl0ocSEmoz9WPUrhu ZLOuIBj8OEC1tpFIQ/qTQyuYV6ZiTHMIIWRGQ6WqMtK3GUqmN8N/bQ2H9MG66KZQXg cq7l8GAF8Byym9XXmjsqYWMHysGmEPo/4tA+0DZs= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Dongli Zhang , Kan Liang , "Peter Zijlstra (Intel)" , Hagar Hemdan Subject: [PATCH 6.6 461/676] perf/x86/intel: Hide Topdown metrics events if the feature is not enumerated Date: Fri, 6 Dec 2024 15:34:40 +0100 Message-ID: <20241206143711.376789131@linuxfoundation.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241206143653.344873888@linuxfoundation.org> References: <20241206143653.344873888@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Kan Liang commit 556a7c039a52c21da33eaae9269984a1ef59189b upstream. The below error is observed on Ice Lake VM. $ perf stat Error: The sys_perf_event_open() syscall returned with 22 (Invalid argument) for event (slots). /bin/dmesg | grep -i perf may provide additional information. In a virtualization env, the Topdown metrics and the slots event haven't been supported yet. The guest CPUID doesn't enumerate them. However, the current kernel unconditionally exposes the slots event and the Topdown metrics events to sysfs, which misleads the perf tool and triggers the error. Hide the perf-metrics topdown events and the slots event if the perf-metrics feature is not enumerated. The big core of a hybrid platform can also supports the perf-metrics feature. Fix the hybrid platform as well. Closes: https://lore.kernel.org/lkml/CAM9d7cj8z+ryyzUHR+P1Dcpot2jjW+Qcc4CPQpfafTXN=LEU0Q@mail.gmail.com/ Reported-by: Dongli Zhang Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Tested-by: Dongli Zhang Link: https://lkml.kernel.org/r/20240708193336.1192217-2-kan.liang@linux.intel.com Signed-off-by: Hagar Hemdan Signed-off-by: Greg Kroah-Hartman --- arch/x86/events/intel/core.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5559,8 +5559,22 @@ default_is_visible(struct kobject *kobj, return attr->mode; } +static umode_t +td_is_visible(struct kobject *kobj, struct attribute *attr, int i) +{ + /* + * Hide the perf metrics topdown events + * if the feature is not enumerated. + */ + if (x86_pmu.num_topdown_events) + return x86_pmu.intel_cap.perf_metrics ? attr->mode : 0; + + return attr->mode; +} + static struct attribute_group group_events_td = { .name = "events", + .is_visible = td_is_visible, }; static struct attribute_group group_events_mem = { @@ -5762,9 +5776,27 @@ static umode_t hybrid_format_is_visible( return (cpu >= 0) && (pmu->cpu_type & pmu_attr->pmu_type) ? attr->mode : 0; } +static umode_t hybrid_td_is_visible(struct kobject *kobj, + struct attribute *attr, int i) +{ + struct device *dev = kobj_to_dev(kobj); + struct x86_hybrid_pmu *pmu = + container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); + + if (!is_attr_for_this_pmu(kobj, attr)) + return 0; + + + /* Only the big core supports perf metrics */ + if (pmu->cpu_type == hybrid_big) + return pmu->intel_cap.perf_metrics ? attr->mode : 0; + + return attr->mode; +} + static struct attribute_group hybrid_group_events_td = { .name = "events", - .is_visible = hybrid_events_is_visible, + .is_visible = hybrid_td_is_visible, }; static struct attribute_group hybrid_group_events_mem = {