From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A6F6149C6F; Fri, 6 Dec 2024 15:19:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733498344; cv=none; b=YhsAPMTe68gh2tVZNGqBPURdpnyyQTEd4Sd316XM0cXaw6pu3WvqHA6UZYykPwWzkSvrlRv6Y91P/zjjUff0pFM1DLUenZcjglfKr7DUkp7aLeoN6XYXIug52eUJBNAjPhPKXo6QKbCwxXNq0Z4j7kDUsOw0wHmx3GFvFso7qcw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733498344; c=relaxed/simple; bh=Nz0uIQANManWfL5ZDSbmeef8Y23XOlmKXOIrjwRLMCA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eNeJo+7uPLzgVpjNTwYLDVlsR5GGtdwtheNABvB/3JN83i1BrZBKSkmE/SvvIwBUlGxUE40j4GhFmM/asGxp+y3K8sH7tbA6od1Qtx2qyz6XOeGrmCIa+PT1GFxnOxB0Hul0TqF+fSr7HctioPGbSeZVnzezA+Kj0YkdJNgBlRw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=ysXPyUbS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="ysXPyUbS" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 042FEC4CED1; Fri, 6 Dec 2024 15:19:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1733498344; bh=Nz0uIQANManWfL5ZDSbmeef8Y23XOlmKXOIrjwRLMCA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ysXPyUbSj3tcagZ5Kx1/BLTaFXGZzqffMtG0q/nfEuOjEG3GRoy44MKACDLTaBsy8 cckfYDyorogN/saMcqqmSQGqCOglr75VHd3vlPIyw3dV+9muW4MCqKn5BR5K8XHjhU F33VKaZDJ32nbvnl/rkKbhQAQwViVdnXZBU6Rrtg= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Mark Rutland , Will Deacon , Catalin Marinas Subject: [PATCH 6.6 525/676] arm64: tls: Fix context-switching of tpidrro_el0 when kpti is enabled Date: Fri, 6 Dec 2024 15:35:44 +0100 Message-ID: <20241206143713.866593067@linuxfoundation.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241206143653.344873888@linuxfoundation.org> References: <20241206143653.344873888@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Will Deacon commit 67ab51cbdfee02ef07fb9d7d14cc0bf6cb5a5e5c upstream. Commit 18011eac28c7 ("arm64: tls: Avoid unconditional zeroing of tpidrro_el0 for native tasks") tried to optimise the context switching of tpidrro_el0 by eliding the clearing of the register when switching to a native task with kpti enabled, on the erroneous assumption that the kpti trampoline entry code would already have taken care of the write. Although the kpti trampoline does zero the register on entry from a native task, the check in tls_thread_switch() is on the *next* task and so we can end up leaving a stale, non-zero value in the register if the previous task was 32-bit. Drop the broken optimisation and zero tpidrro_el0 unconditionally when switching to a native 64-bit task. Cc: Mark Rutland Cc: stable@vger.kernel.org Fixes: 18011eac28c7 ("arm64: tls: Avoid unconditional zeroing of tpidrro_el0 for native tasks") Signed-off-by: Will Deacon Acked-by: Mark Rutland Link: https://lore.kernel.org/r/20241114095332.23391-1-will@kernel.org Signed-off-by: Catalin Marinas Signed-off-by: Greg Kroah-Hartman --- arch/arm64/kernel/process.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -429,7 +429,7 @@ static void tls_thread_switch(struct tas if (is_compat_thread(task_thread_info(next))) write_sysreg(next->thread.uw.tp_value, tpidrro_el0); - else if (!arm64_kernel_unmapped_at_el0()) + else write_sysreg(0, tpidrro_el0); write_sysreg(*task_user_tls(next), tpidr_el0);