From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B2EC20967D; Thu, 12 Dec 2024 17:23:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734024193; cv=none; b=TTfPg8Ko0N+Fo5a3mnX7lQS3FfI5dlDYcVnuxmQKuiZcgn0MQbdIIgvtpC3NAgs2WFHAxugw0y58MKS3z8QSg0RA5JDYcJVkshR5RkJbPA0BA1VCeF9GcVBAIrOHEMHGwHKxZFqOGLXXO8texI5mBmj9+TIZM3kc3rRVx9Hbg/o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734024193; c=relaxed/simple; bh=YSSpMiug4IGr4rJdyeNVFLTIcwT2Zj0wBws1sspL9uo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oy9wgBa/1mvjQ1VfJZtB6ZtlEakxB8giQOxaZWjRP/+hrA07v9HkZ9OCzG2RtYU3+D/aZ63yhkNkDqh1MS4uXiFmShbaVJF9kIGhGkISYOpbzW/ydHYfS5bRWXJSO2enb8T+9fFTLIdAamDObhHuD9otWrasXSWx5DNH+zAcgVM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=GfgF/DkJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="GfgF/DkJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CBDCDC4CECE; Thu, 12 Dec 2024 17:23:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1734024193; bh=YSSpMiug4IGr4rJdyeNVFLTIcwT2Zj0wBws1sspL9uo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GfgF/DkJGCnPw5fOEYsxiI3OSb/WJDwFDfvMM0T0AkJH0xM2D+lZ0KlqyJjZA2uw9 o66PJUd22ETE+6ZkvGZsBljkiUatdp66hRl/Mhmx9HVavDrOIDLrNKGXcQZN9Nd9yz woVQNihq7nIEnTEOt3N7+JfIGY/EsVXdNXIy5rKY= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Nuno Sa , Conor Dooley , Stephen Boyd , Sasha Levin Subject: [PATCH 5.10 187/459] dt-bindings: clock: axi-clkgen: include AXI clk Date: Thu, 12 Dec 2024 15:58:45 +0100 Message-ID: <20241212144300.944556168@linuxfoundation.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241212144253.511169641@linuxfoundation.org> References: <20241212144253.511169641@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.10-stable review patch. If anyone has any objections, please let me know. ------------------ From: Nuno Sa [ Upstream commit 47f3f5a82a31527e027929c5cec3dd1ef5ef30f5 ] In order to access the registers of the HW, we need to make sure that the AXI bus clock is enabled. Hence let's increase the number of clocks by one and add clock-names to differentiate between parent clocks and the bus clock. Fixes: 0e646c52cf0e ("clk: Add axi-clkgen driver") Signed-off-by: Nuno Sa Link: https://lore.kernel.org/r/20241029-axi-clkgen-fix-axiclk-v2-1-bc5e0733ad76@analog.com Reviewed-by: Conor Dooley Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- .../bindings/clock/adi,axi-clkgen.yaml | 22 +++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml index 0d06387184d68..bb2eec3021a09 100644 --- a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml +++ b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml @@ -25,9 +25,21 @@ properties: description: Specifies the reference clock(s) from which the output frequency is derived. This must either reference one clock if only the first clock - input is connected or two if both clock inputs are connected. - minItems: 1 - maxItems: 2 + input is connected or two if both clock inputs are connected. The last + clock is the AXI bus clock that needs to be enabled so we can access the + core registers. + minItems: 2 + maxItems: 3 + + clock-names: + oneOf: + - items: + - const: clkin1 + - const: s_axi_aclk + - items: + - const: clkin1 + - const: clkin2 + - const: s_axi_aclk '#clock-cells': const: 0 @@ -39,6 +51,7 @@ required: - compatible - reg - clocks + - clock-names - '#clock-cells' additionalProperties: false @@ -49,5 +62,6 @@ examples: compatible = "adi,axi-clkgen-2.00.a"; #clock-cells = <0>; reg = <0xff000000 0x1000>; - clocks = <&osc 1>; + clocks = <&osc 1>, <&clkc 15>; + clock-names = "clkin1", "s_axi_aclk"; }; -- 2.43.0