From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2115B21661F; Thu, 12 Dec 2024 15:17:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734016660; cv=none; b=q2dJgAcWS9/iZrfIlznTakmgfiACQsCNp/VJnlzJmCcgrbCkJZGZXPwbxcaODY12xz1qosdXHUlHgMCEZClzlL8a7YyClxlgxAwQM/P8Tntk3Fnc9HzZFqBCPMCmUc7Eq9IokAEow+3Dr99QUXLuz7HZiqWrQJc4Y9zSlttzRyI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734016660; c=relaxed/simple; bh=T/kPJZufyYesoGBjNXPgPeokgh/R7AIysltLw8lSTVE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=H8WNPtxW6NIDXB6RF8Xh0T9CN3PvQFFLrzzAPcx2h7Q8o28QIWgKlMtmllHDltD5l6Xa9gvihO0/7iY10DS0ZPexiMRltluksUCVjYYvgN6HdUs3LKsEQeWpcJS+hHP/x4QVg2nK51JDqswc+CD0BKCxwPusSiQIgnzFaPiOdzc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=s64NYvm7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="s64NYvm7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 825AAC4CECE; Thu, 12 Dec 2024 15:17:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1734016660; bh=T/kPJZufyYesoGBjNXPgPeokgh/R7AIysltLw8lSTVE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=s64NYvm7x/8ReZZdgK9jMzNBVWnpYywuXaUgTVlNES1rOqftyR4jt9y/8wM9+DJ/W XqGJ+zXOljwfTfrF+FLzaipZICzHCjE5KsLiVtXoL3xhJA97LPHZJ7Crd1oyGxiZNC OiPfShdu1eKvALCkmNTbgz2QAZqgb3KHMr0Y5Vzw= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, "Paul E. McKenney" , Breno Leitao , "Peter Zijlstra (Intel)" , Sandipan Das , Sasha Levin Subject: [PATCH 6.12 231/466] perf/x86/amd: Warn only on new bits set Date: Thu, 12 Dec 2024 15:56:40 +0100 Message-ID: <20241212144315.903636428@linuxfoundation.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241212144306.641051666@linuxfoundation.org> References: <20241212144306.641051666@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Breno Leitao [ Upstream commit de20037e1b3c2f2ca97b8c12b8c7bca8abd509a7 ] Warning at every leaking bits can cause a flood of message, triggering various stall-warning mechanisms to fire, including CSD locks, which makes the machine to be unusable. Track the bits that are being leaked, and only warn when a new bit is set. That said, this patch will help with the following issues: 1) It will tell us which bits are being set, so, it is easy to communicate it back to vendor, and to do a root-cause analyzes. 2) It avoid the machine to be unusable, because, worst case scenario, the user gets less than 60 WARNs (one per unhandled bit). Suggested-by: Paul E. McKenney Signed-off-by: Breno Leitao Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Sandipan Das Reviewed-by: Paul E. McKenney Link: https://lkml.kernel.org/r/20241001141020.2620361-1-leitao@debian.org Signed-off-by: Sasha Levin --- arch/x86/events/amd/core.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index 920e3a640cadd..b4a1a2576510e 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -943,11 +943,12 @@ static int amd_pmu_v2_snapshot_branch_stack(struct perf_branch_entry *entries, u static int amd_pmu_v2_handle_irq(struct pt_regs *regs) { struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); + static atomic64_t status_warned = ATOMIC64_INIT(0); + u64 reserved, status, mask, new_bits, prev_bits; struct perf_sample_data data; struct hw_perf_event *hwc; struct perf_event *event; int handled = 0, idx; - u64 reserved, status, mask; bool pmu_enabled; /* @@ -1012,7 +1013,12 @@ static int amd_pmu_v2_handle_irq(struct pt_regs *regs) * the corresponding PMCs are expected to be inactive according to the * active_mask */ - WARN_ON(status > 0); + if (status > 0) { + prev_bits = atomic64_fetch_or(status, &status_warned); + // A new bit was set for the very first time. + new_bits = status & ~prev_bits; + WARN(new_bits, "New overflows for inactive PMCs: %llx\n", new_bits); + } /* Clear overflow and freeze bits */ amd_pmu_ack_global_status(~status); -- 2.43.0