From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E32F8223E93; Thu, 12 Dec 2024 16:58:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734022697; cv=none; b=EsmhRcV+ZfxmpOxo7MF5Ffui7Yyfa/rQTtTg8oStJ5fvvq6OjRoHB9DwRgFpt7APtMv/SQSh+SKGCihMr74Q4S4HpXdG1YHxgEBWs4F76PP1aIhMlwHr3kMTJEQ+eW8FmNiDCr00Mgs2ABDwX1Ssaw1h10d+VjAKgmgVcPUuiSw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734022697; c=relaxed/simple; bh=Clrjdd1fbiemmpiO94t8ztjstgMaHk14H+r9X2ouzH4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XdVQ3N8yjQ4mbSbMwpecrq0TQPqUPEbV7ppA2SHl/N86YTnUlLw1NXnPwGjIIMR3R8waAnPxIY1oRIcSFgwSSkzsrHaoLLsHHajwoXlLI/McDqS/gR5FeSw4E5Fd/95zf4MXt5UGMBAKt421pgtIT+A5LernXzh7yVfgHTvRmYM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=cu5bHHn5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="cu5bHHn5" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1864DC4CECE; Thu, 12 Dec 2024 16:58:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1734022696; bh=Clrjdd1fbiemmpiO94t8ztjstgMaHk14H+r9X2ouzH4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cu5bHHn51p8ibgVDp6U0r9aw7uH9KNqZ0p+v6/wmIQNp2ucQgnQmbmMN7Cg8ZKRId NqleZy4ktjAjMK4utoMm9PcYwD4aKGjkD6Q2GbDUdK7CQrt9f5aCsGPzASt+vxfCQd ZLwyu1S5LkyP5rARRK9NEY1GBaxoOMlICjNijF2g= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Raghavendra Rao Ananta , Marc Zyngier , Oliver Upton Subject: [PATCH 5.15 311/565] KVM: arm64: Ignore PMCNTENSET_EL0 while checking for overflow status Date: Thu, 12 Dec 2024 15:58:26 +0100 Message-ID: <20241212144323.899571767@linuxfoundation.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241212144311.432886635@linuxfoundation.org> References: <20241212144311.432886635@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.15-stable review patch. If anyone has any objections, please let me know. ------------------ From: Raghavendra Rao Ananta commit 54bbee190d42166209185d89070c58a343bf514b upstream. DDI0487K.a D13.3.1 describes the PMU overflow condition, which evaluates to true if any counter's global enable (PMCR_EL0.E), overflow flag (PMOVSSET_EL0[n]), and interrupt enable (PMINTENSET_EL1[n]) are all 1. Of note, this does not require a counter to be enabled (i.e. PMCNTENSET_EL0[n] = 1) to generate an overflow. Align kvm_pmu_overflow_status() with the reality of the architecture and stop using PMCNTENSET_EL0 as part of the overflow condition. The bug was discovered while running an SBSA PMU test [*], which only sets PMCR.E, PMOVSSET<0>, PMINTENSET<0>, and expects an overflow interrupt. Cc: stable@vger.kernel.org Fixes: 76d883c4e640 ("arm64: KVM: Add access handler for PMOVSSET and PMOVSCLR register") Link: https://github.com/ARM-software/sbsa-acs/blob/master/test_pool/pmu/operating_system/test_pmu001.c Signed-off-by: Raghavendra Rao Ananta [ oliver: massaged changelog ] Reviewed-by: Marc Zyngier Link: https://lore.kernel.org/r/20241120005230.2335682-2-oliver.upton@linux.dev Signed-off-by: Oliver Upton Signed-off-by: Greg Kroah-Hartman --- arch/arm64/kvm/pmu-emul.c | 1 - 1 file changed, 1 deletion(-) --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -371,7 +371,6 @@ static u64 kvm_pmu_overflow_status(struc if ((__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E)) { reg = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); - reg &= __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); reg &= __vcpu_sys_reg(vcpu, PMINTENSET_EL1); }