FAILED: patch "[PATCH] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro" failed to apply to 6.6-stable tree

FAILED: patch "[PATCH] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro" failed to apply to 6.6-stable tree

[gregkh]

The patch below does not apply to the 6.6-stable tree.
If someone wants it applied there, or to any other stable or longterm
tree, then please email the backport, including the original git commit
id to <stable@vger.kernel.org>.

To reproduce the conflict and resubmit, you may use the following commands:

git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.6.y
git checkout FETCH_HEAD
git cherry-pick -x 879f70382ff3e92fc854589ada3453e3f5f5b601
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<stable@vger.kernel.org>' --in-reply-to '2025022418-frostlike-congrats-bf0d@gregkh' --subject-prefix 'PATCH 6.6.y' HEAD^..

Possible dependencies:



thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From 879f70382ff3e92fc854589ada3453e3f5f5b601 Mon Sep 17 00:00:00 2001
From: Imre Deak <imre.deak@intel.com>
Date: Fri, 14 Feb 2025 16:19:51 +0200
Subject: [PATCH] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro

The format of the port width field in the DDI_BUF_CTL and the
TRANS_DDI_FUNC_CTL registers are different starting with MTL, where the
x3 lane mode for HDMI FRL has a different encoding in the two registers.
To account for this use the TRANS_DDI_FUNC_CTL's own port width macro.

Cc: <stable@vger.kernel.org> # v6.5+
Fixes: b66a8abaa48a ("drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI")
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-2-imre.deak@intel.com
(cherry picked from commit 76120b3a304aec28fef4910204b81a12db8974da)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index c977b74f82f0..82bf6c654de2 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -809,8 +809,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 		/* select data lane width */
 		tmp = intel_de_read(display,
 				    TRANS_DDI_FUNC_CTL(display, dsi_trans));
-		tmp &= ~DDI_PORT_WIDTH_MASK;
-		tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
+		tmp &= ~TRANS_DDI_PORT_WIDTH_MASK;
+		tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count);
 
 		/* select input pipe */
 		tmp &= ~TRANS_DDI_EDP_INPUT_MASK;

[PATCH 6.6.y] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro

[Imre Deak]

commit 76120b3a304aec28fef4910204b81a12db8974da upstream.

The format of the port width field in the DDI_BUF_CTL and the
TRANS_DDI_FUNC_CTL registers are different starting with MTL, where the
x3 lane mode for HDMI FRL has a different encoding in the two registers.
To account for this use the TRANS_DDI_FUNC_CTL's own port width macro.

Cc: <stable@vger.kernel.org> # v6.5+
Fixes: b66a8abaa48a ("drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI")
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-2-imre.deak@intel.com
(cherry picked from commit 76120b3a304aec28fef4910204b81a12db8974da)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
(cherry picked from commit 879f70382ff3e92fc854589ada3453e3f5f5b601)
[Imre: Rebased on v6.6.y, due to upstream API changes for intel_de_read(),
 TRANS_DDI_FUNC_CTL()]
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 5b8efe8e735a9..0a0efeeb790e2 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -797,8 +797,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 
 		/* select data lane width */
 		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
-		tmp &= ~DDI_PORT_WIDTH_MASK;
-		tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
+		tmp &= ~TRANS_DDI_PORT_WIDTH_MASK;
+		tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count);
 
 		/* select input pipe */
 		tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
-- 
2.44.2

[PATCH 6.6.y] drm/i915/ddi: Fix HDMI port width programming in DDI_BUF_CTL

[Imre Deak]

commit b2ecdabe46d23db275f94cd7c46ca414a144818b upstream.

Fix the port width programming in the DDI_BUF_CTL register on MTLP+,
where this had an off-by-one error.

Cc: <stable@vger.kernel.org> # v6.5+
Fixes: b66a8abaa48a ("drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI")
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-3-imre.deak@intel.com
(cherry picked from commit b2ecdabe46d23db275f94cd7c46ca414a144818b)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
(cherry picked from commit 166ce267ae3f96e439d8ccc838e8ec4d8b4dab73)
[Imre: Rebased on v6.6.y, due to upstream API changes for
 XELPDP_PORT_BUF_CTL1() and addition of the XE2LPD_DDI_BUF_D2D_LINK_ENABLE flag]
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
 drivers/gpu/drm/i915/i915_reg.h          | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b347f90623494..93ad7df1fade9 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3224,7 +3224,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
 		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
 			     XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
 
-		buf_ctl |= DDI_PORT_WIDTH(lane_count);
+		buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count);
 	} else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
 		drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
 		buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aefad14ab27a4..4a50802541a39 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5735,7 +5735,7 @@ enum skl_power_gate {
 #define  DDI_BUF_IS_IDLE			(1 << 7)
 #define  DDI_BUF_CTL_TC_PHY_OWNERSHIP		REG_BIT(6)
 #define  DDI_A_4_LANES				(1 << 4)
-#define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)
+#define  DDI_PORT_WIDTH(width)			(((width) == 3 ? 4 : ((width) - 1)) << 1)
 #define  DDI_PORT_WIDTH_MASK			(7 << 1)
 #define  DDI_PORT_WIDTH_SHIFT			1
 #define  DDI_INIT_DISPLAY_DETECTED		(1 << 0)
-- 
2.44.2

Re: [PATCH 6.6.y] drm/i915/ddi: Fix HDMI port width programming in DDI_BUF_CTL

[Sasha Levin]

[ Sasha's backport helper bot ]

Hi,

Summary of potential issues:
⚠️ Provided upstream commit SHA1 does not match found commit

The claimed upstream commit SHA1 (b2ecdabe46d23db275f94cd7c46ca414a144818b) was not found.
However, I found a matching commit: 166ce267ae3f96e439d8ccc838e8ec4d8b4dab73

Note: The patch differs from the upstream commit:
---
1:  166ce267ae3f9 ! 1:  5dcc143132529 drm/i915/ddi: Fix HDMI port width programming in DDI_BUF_CTL
    @@ Metadata
      ## Commit message ##
         drm/i915/ddi: Fix HDMI port width programming in DDI_BUF_CTL
     
    +    commit b2ecdabe46d23db275f94cd7c46ca414a144818b upstream.
    +
         Fix the port width programming in the DDI_BUF_CTL register on MTLP+,
         where this had an off-by-one error.
     
    @@ Commit message
         Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-3-imre.deak@intel.com
         (cherry picked from commit b2ecdabe46d23db275f94cd7c46ca414a144818b)
         Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
    +    (cherry picked from commit 166ce267ae3f96e439d8ccc838e8ec4d8b4dab73)
    +    [Imre: Rebased on v6.6.y, due to upstream API changes for
    +     XELPDP_PORT_BUF_CTL1() and addition of the XE2LPD_DDI_BUF_D2D_LINK_ENABLE flag]
    +    Signed-off-by: Imre Deak <imre.deak@intel.com>
     
      ## drivers/gpu/drm/i915/display/intel_ddi.c ##
    -@@ drivers/gpu/drm/i915/display/intel_ddi.c: static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
    - 		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port),
    +@@ drivers/gpu/drm/i915/display/intel_ddi.c: static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
    + 		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
      			     XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
      
     -		buf_ctl |= DDI_PORT_WIDTH(lane_count);
     +		buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count);
    - 
    - 		if (DISPLAY_VER(dev_priv) >= 20)
    - 			buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
    + 	} else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
    + 		drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
    + 		buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
     
      ## drivers/gpu/drm/i915/i915_reg.h ##
     @@ drivers/gpu/drm/i915/i915_reg.h: enum skl_power_gate {
---

Results of testing on various branches:

| Branch                    | Patch Apply | Build Test |
|---------------------------|-------------|------------|
| stable/linux-6.6.y        |  Success    |  Success   |

Re: [PATCH 6.6.y] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro

[Sasha Levin]

[ Sasha's backport helper bot ]

Hi,

Summary of potential issues:
⚠️ Provided upstream commit SHA1 does not match found commit

The claimed upstream commit SHA1 (76120b3a304aec28fef4910204b81a12db8974da) was not found.
However, I found a matching commit: 879f70382ff3e92fc854589ada3453e3f5f5b601

Note: The patch differs from the upstream commit:
---
1:  879f70382ff3e ! 1:  b3874f246c67b drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro
    @@ Metadata
      ## Commit message ##
         drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro
     
    +    commit 76120b3a304aec28fef4910204b81a12db8974da upstream.
    +
         The format of the port width field in the DDI_BUF_CTL and the
         TRANS_DDI_FUNC_CTL registers are different starting with MTL, where the
         x3 lane mode for HDMI FRL has a different encoding in the two registers.
    @@ Commit message
         Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-2-imre.deak@intel.com
         (cherry picked from commit 76120b3a304aec28fef4910204b81a12db8974da)
         Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
    +    (cherry picked from commit 879f70382ff3e92fc854589ada3453e3f5f5b601)
    +    [Imre: Rebased on v6.6.y, due to upstream API changes for intel_de_read(),
    +     TRANS_DDI_FUNC_CTL()]
    +    Signed-off-by: Imre Deak <imre.deak@intel.com>
     
      ## drivers/gpu/drm/i915/display/icl_dsi.c ##
     @@ drivers/gpu/drm/i915/display/icl_dsi.c: gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
    + 
      		/* select data lane width */
    - 		tmp = intel_de_read(display,
    - 				    TRANS_DDI_FUNC_CTL(display, dsi_trans));
    + 		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
     -		tmp &= ~DDI_PORT_WIDTH_MASK;
     -		tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
     +		tmp &= ~TRANS_DDI_PORT_WIDTH_MASK;
---

Results of testing on various branches:

| Branch                    | Patch Apply | Build Test |
|---------------------------|-------------|------------|
| stable/linux-6.6.y        |  Success    |  Success   |

Re: [PATCH 6.6.y] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro

[Imre Deak]

Hi,

On Tue, Feb 25, 2025 at 11:13:59AM -0500, Sasha Levin wrote:
> [ Sasha's backport helper bot ]
> 
> Hi,
> 
> Summary of potential issues:
> ⚠️ Provided upstream commit SHA1 does not match found commit
> 
> The claimed upstream commit SHA1 (76120b3a304aec28fef4910204b81a12db8974da) was not found.
> However, I found a matching commit: 879f70382ff3e92fc854589ada3453e3f5f5b601

thanks for the report. The original commit is 76120b3a304a (see [1]),
but indeed it's not upstream yet, as it was merged to the drm-intel-next
branch which will be only part of a later drm pull request.

Since the change is a fix it was also cherry-picked to drm-intel-fixes
as 879f70382ff3 and merged upstream via an earlier drm-fixes pull
request.

The same happened in two other backports I sent (see [2] and [3]).

> Note: The patch differs from the upstream commit:

The patches differ from the upstream ones, as they had to be rebased due
to upstream changes that are not in the stable trees.

Is it ok if I resend this and [2], [3], with the commit ... upstream
lines changed to the SHA1 actually upstream (166ce267ae3f for [2] and
879f70382ff3 for this and [3])?

Thanks,
Imre

[1] https://cgit.freedesktop.org/drm-intel/commit/?h=drm-intel-next&id=76120b3a304aec28fef4910204b81a12db8974da
[2] https://lore.kernel.org/stable/20250225091539-d02fffb8792ca6dd@stable.kernel.org
[3] https://lore.kernel.org/stable/20250225092150-aa652f5ea80fe710@stable.kernel.org

> ---
> 1:  879f70382ff3e ! 1:  b3874f246c67b drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro
>     @@ Metadata
>       ## Commit message ##
>          drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro
>      
>     +    commit 76120b3a304aec28fef4910204b81a12db8974da upstream.
>     +
>          The format of the port width field in the DDI_BUF_CTL and the
>          TRANS_DDI_FUNC_CTL registers are different starting with MTL, where the
>          x3 lane mode for HDMI FRL has a different encoding in the two registers.
>     @@ Commit message
>          Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-2-imre.deak@intel.com
>          (cherry picked from commit 76120b3a304aec28fef4910204b81a12db8974da)
>          Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>     +    (cherry picked from commit 879f70382ff3e92fc854589ada3453e3f5f5b601)
>     +    [Imre: Rebased on v6.6.y, due to upstream API changes for intel_de_read(),
>     +     TRANS_DDI_FUNC_CTL()]
>     +    Signed-off-by: Imre Deak <imre.deak@intel.com>
>      
>       ## drivers/gpu/drm/i915/display/icl_dsi.c ##
>      @@ drivers/gpu/drm/i915/display/icl_dsi.c: gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
>     + 
>       		/* select data lane width */
>     - 		tmp = intel_de_read(display,
>     - 				    TRANS_DDI_FUNC_CTL(display, dsi_trans));
>     + 		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
>      -		tmp &= ~DDI_PORT_WIDTH_MASK;
>      -		tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
>      +		tmp &= ~TRANS_DDI_PORT_WIDTH_MASK;
> ---
> 
> Results of testing on various branches:
> 
> | Branch                    | Patch Apply | Build Test |
> |---------------------------|-------------|------------|
> | stable/linux-6.6.y        |  Success    |  Success   |

Re: [PATCH 6.6.y] drm/i915/ddi: Fix HDMI port width programming in DDI_BUF_CTL

[Greg KH]

On Mon, Feb 24, 2025 at 05:31:12PM +0200, Imre Deak wrote:
> commit b2ecdabe46d23db275f94cd7c46ca414a144818b upstream.

Again, this is not an upstream commit id.

Re: [PATCH 6.6.y] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro

[Greg KH]

On Mon, Feb 24, 2025 at 05:31:11PM +0200, Imre Deak wrote:
> commit 76120b3a304aec28fef4910204b81a12db8974da upstream.

Not an upstream commit id.

[PATCH 1/2] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro

[Imre Deak]

commit 879f70382ff3e92fc854589ada3453e3f5f5b601 upstream.

The format of the port width field in the DDI_BUF_CTL and the
TRANS_DDI_FUNC_CTL registers are different starting with MTL, where the
x3 lane mode for HDMI FRL has a different encoding in the two registers.
To account for this use the TRANS_DDI_FUNC_CTL's own port width macro.

Cc: <stable@vger.kernel.org> # v6.5+
Fixes: b66a8abaa48a ("drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI")
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-2-imre.deak@intel.com
(cherry picked from commit 76120b3a304aec28fef4910204b81a12db8974da)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
(cherry picked from commit 879f70382ff3e92fc854589ada3453e3f5f5b601)
[Imre: Rebased on v6.6.y, due to upstream API changes for intel_de_read(),
 TRANS_DDI_FUNC_CTL()]
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 5b8efe8e735a9..0a0efeeb790e2 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -797,8 +797,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 
 		/* select data lane width */
 		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
-		tmp &= ~DDI_PORT_WIDTH_MASK;
-		tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
+		tmp &= ~TRANS_DDI_PORT_WIDTH_MASK;
+		tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count);
 
 		/* select input pipe */
 		tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
-- 
2.44.2