From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E7A11946C7; Wed, 5 Mar 2025 17:50:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741197025; cv=none; b=pm0FBoB0Owj/KQLL1NcjI7z1QQzhZZaxefayzCtCVuv3XmLic7Iu/JyLc50xCBMfme05Kuzbufq0caJxSfrF2o+JdaHI/YsBSK/J55MNfWZYVy7n7zA2YIfJxbp5v9/DTpQ8+yHbXUixBe4RuYyUxeddvZrBEXmrva9s9ZoR0X4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741197025; c=relaxed/simple; bh=VxPTycoYH2/qyyOIZnCkm7vM7Sny3NTs2TK4kx6yRAw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AKmFqh9vdH8qCgPezlqojyKV/ZlDi2s6GJ9Vp+6P77Cf6P2VeWgWF34wMLGoakpEvApecASkUbCz5/bK0Z0SAiuicdO4jq6to9uk+37tEUmZKigXzJdX0s/dQLjjiMkbFgbkP4Y+LMH9uiMSByzpVqd8nYS2EjzXpMlPPycmsjk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=r2cHoBUJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="r2cHoBUJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A9CC0C4CED1; Wed, 5 Mar 2025 17:50:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1741197025; bh=VxPTycoYH2/qyyOIZnCkm7vM7Sny3NTs2TK4kx6yRAw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=r2cHoBUJYSoQp31b/phXvlqOmexUcFQhWoiBMsDBfuLATuH21dcJjcl+0chMlTUkY d5P1x6obr0EtKkBvtMYmH3zT+ToZod3lyjjnx9pn4jReQfdD2h2N0ku3i6Zl71Tdic WXg4tMwya5w4188Q2lkuZ/p4aljZCeeqixyubol4= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Hari.PrasathGE@microchip.com, Mahesh.Abotula@microchip.com, Marco.Cardellini@microchip.com, =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= , Mark Brown , Sasha Levin Subject: [PATCH 6.1 014/176] spi: atmel-qspi: Memory barriers after memory-mapped I/O Date: Wed, 5 Mar 2025 18:46:23 +0100 Message-ID: <20250305174506.033524782@linuxfoundation.org> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250305174505.437358097@linuxfoundation.org> References: <20250305174505.437358097@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 6.1-stable review patch. If anyone has any objections, please let me know. ------------------ From: Bence Csókás [ Upstream commit be92ab2de0ee1a13291c3b47b2d7eb24d80c0a2c ] The QSPI peripheral control and status registers are accessible via the SoC's APB bus, whereas MMIO transactions' data travels on the AHB bus. Microchip documentation and even sample code from Atmel emphasises the need for a memory barrier before the first MMIO transaction to the AHB-connected QSPI, and before the last write to its registers via APB. This is achieved by the following lines in `atmel_qspi_transfer()`: /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */ (void)atmel_qspi_read(aq, QSPI_IFR); However, the current documentation makes no mention to synchronization requirements in the other direction, i.e. after the last data written via AHB, and before the first register access on APB. In our case, we were facing an issue where the QSPI peripheral would cease to send any new CSR (nCS Rise) interrupts, leading to a timeout in `atmel_qspi_wait_for_completion()` and ultimately this panic in higher levels: ubi0 error: ubi_io_write: error -110 while writing 63108 bytes to PEB 491:128, written 63104 bytes After months of extensive research of the codebase, fiddling around the debugger with kgdb, and back-and-forth with Microchip, we came to the conclusion that the issue is probably that the peripheral is still busy receiving on AHB when the LASTXFER bit is written to its Control Register on APB, therefore this write gets lost, and the peripheral still thinks there is more data to come in the MMIO transfer. This was first formulated when we noticed that doubling the write() of QSPI_CR_LASTXFER seemed to solve the problem. Ultimately, the solution is to introduce memory barriers after the AHB-mapped MMIO transfers, to ensure ordering. Fixes: d5433def3153 ("mtd: spi-nor: atmel-quadspi: Add spi-mem support to atmel-quadspi") Cc: Hari.PrasathGE@microchip.com Cc: Mahesh.Abotula@microchip.com Cc: Marco.Cardellini@microchip.com Cc: stable@vger.kernel.org # c0a0203cf579: ("spi: atmel-quadspi: Create `atmel_qspi_ops`"...) Cc: stable@vger.kernel.org # 6.x.y Signed-off-by: Bence Csókás Link: https://patch.msgid.link/20241219091258.395187-1-csokas.bence@prolan.hu Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/spi/atmel-quadspi.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 32fcab2a11885..a62baef08e6a8 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -454,13 +454,20 @@ static int atmel_qspi_transfer(struct spi_mem *mem, (void)atmel_qspi_read(aq, QSPI_IFR); /* Send/Receive data */ - if (op->data.dir == SPI_MEM_DATA_IN) + if (op->data.dir == SPI_MEM_DATA_IN) { memcpy_fromio(op->data.buf.in, aq->mem + offset, op->data.nbytes); - else + + /* Synchronize AHB and APB accesses again */ + rmb(); + } else { memcpy_toio(aq->mem + offset, op->data.buf.out, op->data.nbytes); + /* Synchronize AHB and APB accesses again */ + wmb(); + } + /* Release the chip-select */ atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR); -- 2.39.5