public inbox for stable@vger.kernel.org
 help / color / mirror / Atom feed
* FAILED: patch "[PATCH] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro" failed to apply to 6.12-stable tree
@ 2025-02-24 10:22 gregkh
  2025-02-24 15:39 ` [PATCH 6.12.y] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro Imre Deak
  2025-03-05 15:50 ` Imre Deak
  0 siblings, 2 replies; 6+ messages in thread
From: gregkh @ 2025-02-24 10:22 UTC (permalink / raw)
  To: imre.deak, jani.nikula, rodrigo.vivi, stable; +Cc: stable


The patch below does not apply to the 6.12-stable tree.
If someone wants it applied there, or to any other stable or longterm
tree, then please email the backport, including the original git commit
id to <stable@vger.kernel.org>.

To reproduce the conflict and resubmit, you may use the following commands:

git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.12.y
git checkout FETCH_HEAD
git cherry-pick -x 879f70382ff3e92fc854589ada3453e3f5f5b601
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<stable@vger.kernel.org>' --in-reply-to '2025022418-clergyman-hacker-f7f7@gregkh' --subject-prefix 'PATCH 6.12.y' HEAD^..

Possible dependencies:



thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From 879f70382ff3e92fc854589ada3453e3f5f5b601 Mon Sep 17 00:00:00 2001
From: Imre Deak <imre.deak@intel.com>
Date: Fri, 14 Feb 2025 16:19:51 +0200
Subject: [PATCH] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro

The format of the port width field in the DDI_BUF_CTL and the
TRANS_DDI_FUNC_CTL registers are different starting with MTL, where the
x3 lane mode for HDMI FRL has a different encoding in the two registers.
To account for this use the TRANS_DDI_FUNC_CTL's own port width macro.

Cc: <stable@vger.kernel.org> # v6.5+
Fixes: b66a8abaa48a ("drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI")
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-2-imre.deak@intel.com
(cherry picked from commit 76120b3a304aec28fef4910204b81a12db8974da)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index c977b74f82f0..82bf6c654de2 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -809,8 +809,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 		/* select data lane width */
 		tmp = intel_de_read(display,
 				    TRANS_DDI_FUNC_CTL(display, dsi_trans));
-		tmp &= ~DDI_PORT_WIDTH_MASK;
-		tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
+		tmp &= ~TRANS_DDI_PORT_WIDTH_MASK;
+		tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count);
 
 		/* select input pipe */
 		tmp &= ~TRANS_DDI_EDP_INPUT_MASK;


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH 6.12.y] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro
  2025-02-24 10:22 FAILED: patch "[PATCH] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro" failed to apply to 6.12-stable tree gregkh
@ 2025-02-24 15:39 ` Imre Deak
  2025-02-25 16:13   ` Sasha Levin
  2025-03-05 12:57   ` Greg KH
  2025-03-05 15:50 ` Imre Deak
  1 sibling, 2 replies; 6+ messages in thread
From: Imre Deak @ 2025-02-24 15:39 UTC (permalink / raw)
  To: stable; +Cc: Jani Nikula, Rodrigo Vivi

commit 76120b3a304aec28fef4910204b81a12db8974da upstream.

The format of the port width field in the DDI_BUF_CTL and the
TRANS_DDI_FUNC_CTL registers are different starting with MTL, where the
x3 lane mode for HDMI FRL has a different encoding in the two registers.
To account for this use the TRANS_DDI_FUNC_CTL's own port width macro.

Cc: <stable@vger.kernel.org> # v6.5+
Fixes: b66a8abaa48a ("drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI")
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-2-imre.deak@intel.com
(cherry picked from commit 76120b3a304aec28fef4910204b81a12db8974da)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
(cherry picked from commit 879f70382ff3e92fc854589ada3453e3f5f5b601)
[Imre: Rebased on v6.12.y, due to upstream API changes in
 intel_de_read(), TRANS_DDI_FUNC_CTL()]
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 293efc1f841df..834ec19b303d5 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -800,8 +800,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 		/* select data lane width */
 		tmp = intel_de_read(dev_priv,
 				    TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
-		tmp &= ~DDI_PORT_WIDTH_MASK;
-		tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
+		tmp &= ~TRANS_DDI_PORT_WIDTH_MASK;
+		tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count);
 
 		/* select input pipe */
 		tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
-- 
2.44.2


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH 6.12.y] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro
  2025-02-24 15:39 ` [PATCH 6.12.y] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro Imre Deak
@ 2025-02-25 16:13   ` Sasha Levin
  2025-03-05 12:57   ` Greg KH
  1 sibling, 0 replies; 6+ messages in thread
From: Sasha Levin @ 2025-02-25 16:13 UTC (permalink / raw)
  To: stable, imre.deak; +Cc: Sasha Levin

[ Sasha's backport helper bot ]

Hi,

Summary of potential issues:
⚠️ Provided upstream commit SHA1 does not match found commit
ℹ️ Patch is missing in 6.13.y (ignore if backport was sent)
⚠️ Commit missing in all newer stable branches

The claimed upstream commit SHA1 (76120b3a304aec28fef4910204b81a12db8974da) was not found.
However, I found a matching commit: 879f70382ff3e92fc854589ada3453e3f5f5b601

Status in newer kernel trees:
6.13.y | Not found
6.6.y | Not found

Note: The patch differs from the upstream commit:
---
1:  879f70382ff3e ! 1:  087834a498981 drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro
    @@ Metadata
      ## Commit message ##
         drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro
     
    +    commit 76120b3a304aec28fef4910204b81a12db8974da upstream.
    +
         The format of the port width field in the DDI_BUF_CTL and the
         TRANS_DDI_FUNC_CTL registers are different starting with MTL, where the
         x3 lane mode for HDMI FRL has a different encoding in the two registers.
    @@ Commit message
         Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-2-imre.deak@intel.com
         (cherry picked from commit 76120b3a304aec28fef4910204b81a12db8974da)
         Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
    +    (cherry picked from commit 879f70382ff3e92fc854589ada3453e3f5f5b601)
    +    [Imre: Rebased on v6.12.y, due to upstream API changes in
    +     intel_de_read(), TRANS_DDI_FUNC_CTL()]
    +    Signed-off-by: Imre Deak <imre.deak@intel.com>
     
      ## drivers/gpu/drm/i915/display/icl_dsi.c ##
     @@ drivers/gpu/drm/i915/display/icl_dsi.c: gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
      		/* select data lane width */
    - 		tmp = intel_de_read(display,
    - 				    TRANS_DDI_FUNC_CTL(display, dsi_trans));
    + 		tmp = intel_de_read(dev_priv,
    + 				    TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
     -		tmp &= ~DDI_PORT_WIDTH_MASK;
     -		tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
     +		tmp &= ~TRANS_DDI_PORT_WIDTH_MASK;
---

Results of testing on various branches:

| Branch                    | Patch Apply | Build Test |
|---------------------------|-------------|------------|
| stable/linux-6.12.y       |  Success    |  Success   |

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 6.12.y] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro
  2025-02-24 15:39 ` [PATCH 6.12.y] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro Imre Deak
  2025-02-25 16:13   ` Sasha Levin
@ 2025-03-05 12:57   ` Greg KH
  1 sibling, 0 replies; 6+ messages in thread
From: Greg KH @ 2025-03-05 12:57 UTC (permalink / raw)
  To: Imre Deak; +Cc: stable, Jani Nikula, Rodrigo Vivi

On Mon, Feb 24, 2025 at 05:39:10PM +0200, Imre Deak wrote:
> commit 76120b3a304aec28fef4910204b81a12db8974da upstream.

No, sorry, this needs to be the commit in Linus's tree, not in a stable
kernel tree, as a stable kernel tree is NOT "upstream".

Please fix up and resend.

thanks,

greg k-h

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 6.12.y] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro
  2025-02-24 10:22 FAILED: patch "[PATCH] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro" failed to apply to 6.12-stable tree gregkh
  2025-02-24 15:39 ` [PATCH 6.12.y] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro Imre Deak
@ 2025-03-05 15:50 ` Imre Deak
  2025-03-06 19:11   ` Sasha Levin
  1 sibling, 1 reply; 6+ messages in thread
From: Imre Deak @ 2025-03-05 15:50 UTC (permalink / raw)
  To: stable; +Cc: Jani Nikula, Rodrigo Vivi

commit 879f70382ff3e92fc854589ada3453e3f5f5b601 upstream.

The format of the port width field in the DDI_BUF_CTL and the
TRANS_DDI_FUNC_CTL registers are different starting with MTL, where the
x3 lane mode for HDMI FRL has a different encoding in the two registers.
To account for this use the TRANS_DDI_FUNC_CTL's own port width macro.

Cc: <stable@vger.kernel.org> # v6.5+
Fixes: b66a8abaa48a ("drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI")
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-2-imre.deak@intel.com
(cherry picked from commit 76120b3a304aec28fef4910204b81a12db8974da)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
(cherry picked from commit 879f70382ff3e92fc854589ada3453e3f5f5b601)
[Imre: Rebased on v6.12.y, due to upstream API changes in
 intel_de_read(), TRANS_DDI_FUNC_CTL()]
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 293efc1f841df..834ec19b303d5 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -800,8 +800,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 		/* select data lane width */
 		tmp = intel_de_read(dev_priv,
 				    TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
-		tmp &= ~DDI_PORT_WIDTH_MASK;
-		tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
+		tmp &= ~TRANS_DDI_PORT_WIDTH_MASK;
+		tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count);
 
 		/* select input pipe */
 		tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
-- 
2.44.2


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH 6.12.y] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro
  2025-03-05 15:50 ` Imre Deak
@ 2025-03-06 19:11   ` Sasha Levin
  0 siblings, 0 replies; 6+ messages in thread
From: Sasha Levin @ 2025-03-06 19:11 UTC (permalink / raw)
  To: stable, imre.deak; +Cc: Sasha Levin

[ Sasha's backport helper bot ]

Hi,

Summary of potential issues:
ℹ️ Patch is missing in 6.13.y (ignore if backport was sent)
⚠️ Commit missing in all newer stable branches

The upstream commit SHA1 provided is correct: 879f70382ff3e92fc854589ada3453e3f5f5b601

Status in newer kernel trees:
6.13.y | Present (different SHA1: d636772d1796)
6.6.y | Not found

Note: The patch differs from the upstream commit:
---
1:  879f70382ff3e ! 1:  616483933e167 drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro
    @@ Metadata
      ## Commit message ##
         drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro
     
    +    commit 879f70382ff3e92fc854589ada3453e3f5f5b601 upstream.
    +
         The format of the port width field in the DDI_BUF_CTL and the
         TRANS_DDI_FUNC_CTL registers are different starting with MTL, where the
         x3 lane mode for HDMI FRL has a different encoding in the two registers.
    @@ Commit message
         Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-2-imre.deak@intel.com
         (cherry picked from commit 76120b3a304aec28fef4910204b81a12db8974da)
         Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
    +    (cherry picked from commit 879f70382ff3e92fc854589ada3453e3f5f5b601)
    +    [Imre: Rebased on v6.12.y, due to upstream API changes in
    +     intel_de_read(), TRANS_DDI_FUNC_CTL()]
    +    Signed-off-by: Imre Deak <imre.deak@intel.com>
     
      ## drivers/gpu/drm/i915/display/icl_dsi.c ##
     @@ drivers/gpu/drm/i915/display/icl_dsi.c: gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
      		/* select data lane width */
    - 		tmp = intel_de_read(display,
    - 				    TRANS_DDI_FUNC_CTL(display, dsi_trans));
    + 		tmp = intel_de_read(dev_priv,
    + 				    TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
     -		tmp &= ~DDI_PORT_WIDTH_MASK;
     -		tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
     +		tmp &= ~TRANS_DDI_PORT_WIDTH_MASK;
---

Results of testing on various branches:

| Branch                    | Patch Apply | Build Test |
|---------------------------|-------------|------------|
| stable/linux-6.12.y       |  Success    |  Success   |

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2025-03-06 19:11 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-02-24 10:22 FAILED: patch "[PATCH] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro" failed to apply to 6.12-stable tree gregkh
2025-02-24 15:39 ` [PATCH 6.12.y] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro Imre Deak
2025-02-25 16:13   ` Sasha Levin
2025-03-05 12:57   ` Greg KH
2025-03-05 15:50 ` Imre Deak
2025-03-06 19:11   ` Sasha Levin

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox