* [PATCH net v2 1/2] net: phy: nxp-c45-tja11xx: add TJA112X PHY configuration errata [not found] <20250304160619.181046-1-andrei.botila@oss.nxp.com> @ 2025-03-04 16:06 ` Andrei Botila 2025-03-06 9:43 ` Paolo Abeni 2025-03-04 16:06 ` [PATCH net v2 2/2] net: phy: nxp-c45-tja11xx: add TJA112XB SGMII PCS restart errata Andrei Botila 1 sibling, 1 reply; 7+ messages in thread From: Andrei Botila @ 2025-03-04 16:06 UTC (permalink / raw) To: Andrew Lunn, Heiner Kallweit, Russell King, David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni Cc: netdev, linux-kernel, s32, Christophe Lizzi, Alberto Ruiz, Enric Balletbo, Andrei Botila, stable The most recent sillicon versions of TJA1120 and TJA1121 can achieve full silicon performance by putting the PHY in managed mode. It is necessary to apply these PHY writes before link gets established. Application of this fix is required after restart of device and wakeup from sleep. Cc: stable@vger.kernel.org Fixes: f1fe5dff2b8a ("net: phy: nxp-c45-tja11xx: add TJA1120 support") Signed-off-by: Andrei Botila <andrei.botila@oss.nxp.com> --- drivers/net/phy/nxp-c45-tja11xx.c | 52 +++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c index 34231b5b9175..709d6c9f7cba 100644 --- a/drivers/net/phy/nxp-c45-tja11xx.c +++ b/drivers/net/phy/nxp-c45-tja11xx.c @@ -22,6 +22,11 @@ #define PHY_ID_TJA_1103 0x001BB010 #define PHY_ID_TJA_1120 0x001BB031 +#define VEND1_DEVICE_ID3 0x0004 +#define TJA1120_DEV_ID3_SILICON_VERSION GENMASK(15, 12) +#define TJA1120_DEV_ID3_SAMPLE_TYPE GENMASK(11, 8) +#define DEVICE_ID3_SAMPLE_TYPE_R 0x9 + #define VEND1_DEVICE_CONTROL 0x0040 #define DEVICE_CONTROL_RESET BIT(15) #define DEVICE_CONTROL_CONFIG_GLOBAL_EN BIT(14) @@ -1593,6 +1598,50 @@ static int nxp_c45_set_phy_mode(struct phy_device *phydev) return 0; } +/* Errata: ES_TJA1120 and ES_TJA1121 Rev. 1.0 — 28 November 2024 Section 3.1 */ +static void nxp_c45_tja1120_errata(struct phy_device *phydev) +{ + int silicon_version, sample_type; + bool macsec_ability; + int phy_abilities; + int ret = 0; + + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_ID3); + if (ret < 0) + return; + + sample_type = FIELD_GET(TJA1120_DEV_ID3_SAMPLE_TYPE, ret); + if (sample_type != DEVICE_ID3_SAMPLE_TYPE_R) + return; + + silicon_version = FIELD_GET(TJA1120_DEV_ID3_SILICON_VERSION, ret); + + phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1, + VEND1_PORT_ABILITIES); + macsec_ability = !!(phy_abilities & MACSEC_ABILITY); + if ((!macsec_ability && silicon_version == 2) || + (macsec_ability && silicon_version == 1)) { + /* TJA1120/TJA1121 PHY configuration errata workaround. + * Apply PHY writes sequence before link up. + */ + if (!macsec_ability) { + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x4b95); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0xf3cd); + } else { + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x89c7); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0893); + } + + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0476, 0x58a0); + + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x8921, 0xa3a); + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x89F1, 0x16c1); + + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0); + } +} + static int nxp_c45_config_init(struct phy_device *phydev) { int ret; @@ -1609,6 +1658,9 @@ static int nxp_c45_config_init(struct phy_device *phydev) phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 1); phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 2); + if (phy_id_compare(phydev->phy_id, PHY_ID_TJA_1120, GENMASK(31, 4))) + nxp_c45_tja1120_errata(phydev); + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG, PHY_CONFIG_AUTO); -- 2.48.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH net v2 1/2] net: phy: nxp-c45-tja11xx: add TJA112X PHY configuration errata 2025-03-04 16:06 ` [PATCH net v2 1/2] net: phy: nxp-c45-tja11xx: add TJA112X PHY configuration errata Andrei Botila @ 2025-03-06 9:43 ` Paolo Abeni 2025-03-06 12:03 ` Andrei Botila 0 siblings, 1 reply; 7+ messages in thread From: Paolo Abeni @ 2025-03-06 9:43 UTC (permalink / raw) To: Andrei Botila, Andrew Lunn, Heiner Kallweit, Russell King, David S. Miller, Eric Dumazet, Jakub Kicinski Cc: netdev, linux-kernel, s32, Christophe Lizzi, Alberto Ruiz, Enric Balletbo, stable On 3/4/25 5:06 PM, Andrei Botila wrote: > diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c > index 34231b5b9175..709d6c9f7cba 100644 > --- a/drivers/net/phy/nxp-c45-tja11xx.c > +++ b/drivers/net/phy/nxp-c45-tja11xx.c > @@ -22,6 +22,11 @@ > #define PHY_ID_TJA_1103 0x001BB010 > #define PHY_ID_TJA_1120 0x001BB031 > > +#define VEND1_DEVICE_ID3 0x0004 > +#define TJA1120_DEV_ID3_SILICON_VERSION GENMASK(15, 12) > +#define TJA1120_DEV_ID3_SAMPLE_TYPE GENMASK(11, 8) > +#define DEVICE_ID3_SAMPLE_TYPE_R 0x9 > + > #define VEND1_DEVICE_CONTROL 0x0040 > #define DEVICE_CONTROL_RESET BIT(15) > #define DEVICE_CONTROL_CONFIG_GLOBAL_EN BIT(14) > @@ -1593,6 +1598,50 @@ static int nxp_c45_set_phy_mode(struct phy_device *phydev) > return 0; > } > > +/* Errata: ES_TJA1120 and ES_TJA1121 Rev. 1.0 — 28 November 2024 Section 3.1 */ > +static void nxp_c45_tja1120_errata(struct phy_device *phydev) > +{ > + int silicon_version, sample_type; > + bool macsec_ability; > + int phy_abilities; > + int ret = 0; > + > + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_ID3); > + if (ret < 0) > + return; > + > + sample_type = FIELD_GET(TJA1120_DEV_ID3_SAMPLE_TYPE, ret); > + if (sample_type != DEVICE_ID3_SAMPLE_TYPE_R) > + return; > + > + silicon_version = FIELD_GET(TJA1120_DEV_ID3_SILICON_VERSION, ret); > + > + phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1, > + VEND1_PORT_ABILITIES); > + macsec_ability = !!(phy_abilities & MACSEC_ABILITY); > + if ((!macsec_ability && silicon_version == 2) || > + (macsec_ability && silicon_version == 1)) { > + /* TJA1120/TJA1121 PHY configuration errata workaround. > + * Apply PHY writes sequence before link up. > + */ > + if (!macsec_ability) { > + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x4b95); > + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0xf3cd); > + } else { > + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x89c7); > + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0893); > + } > + > + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0476, 0x58a0); > + > + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x8921, 0xa3a); > + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x89F1, 0x16c1); > + > + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0); > + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0); Please add macro with meaningful names for all the magic numbers used above, thanks! Paolo ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH net v2 1/2] net: phy: nxp-c45-tja11xx: add TJA112X PHY configuration errata 2025-03-06 9:43 ` Paolo Abeni @ 2025-03-06 12:03 ` Andrei Botila 2025-03-06 15:35 ` Andrew Lunn 0 siblings, 1 reply; 7+ messages in thread From: Andrei Botila @ 2025-03-06 12:03 UTC (permalink / raw) To: Paolo Abeni, Andrew Lunn, Heiner Kallweit, Russell King, David S. Miller, Eric Dumazet, Jakub Kicinski Cc: netdev, linux-kernel, s32, Christophe Lizzi, Alberto Ruiz, Enric Balletbo, stable On 3/6/2025 11:43 AM, Paolo Abeni wrote: > On 3/4/25 5:06 PM, Andrei Botila wrote: >> diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c >> index 34231b5b9175..709d6c9f7cba 100644 >> --- a/drivers/net/phy/nxp-c45-tja11xx.c >> +++ b/drivers/net/phy/nxp-c45-tja11xx.c >> @@ -22,6 +22,11 @@ >> #define PHY_ID_TJA_1103 0x001BB010 >> #define PHY_ID_TJA_1120 0x001BB031 >> >> +#define VEND1_DEVICE_ID3 0x0004 >> +#define TJA1120_DEV_ID3_SILICON_VERSION GENMASK(15, 12) >> +#define TJA1120_DEV_ID3_SAMPLE_TYPE GENMASK(11, 8) >> +#define DEVICE_ID3_SAMPLE_TYPE_R 0x9 >> + >> #define VEND1_DEVICE_CONTROL 0x0040 >> #define DEVICE_CONTROL_RESET BIT(15) >> #define DEVICE_CONTROL_CONFIG_GLOBAL_EN BIT(14) >> @@ -1593,6 +1598,50 @@ static int nxp_c45_set_phy_mode(struct phy_device *phydev) >> return 0; >> } >> >> +/* Errata: ES_TJA1120 and ES_TJA1121 Rev. 1.0 — 28 November 2024 Section 3.1 */ >> +static void nxp_c45_tja1120_errata(struct phy_device *phydev) >> +{ >> + int silicon_version, sample_type; >> + bool macsec_ability; >> + int phy_abilities; >> + int ret = 0; >> + >> + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_ID3); >> + if (ret < 0) >> + return; >> + >> + sample_type = FIELD_GET(TJA1120_DEV_ID3_SAMPLE_TYPE, ret); >> + if (sample_type != DEVICE_ID3_SAMPLE_TYPE_R) >> + return; >> + >> + silicon_version = FIELD_GET(TJA1120_DEV_ID3_SILICON_VERSION, ret); >> + >> + phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1, >> + VEND1_PORT_ABILITIES); >> + macsec_ability = !!(phy_abilities & MACSEC_ABILITY); >> + if ((!macsec_ability && silicon_version == 2) || >> + (macsec_ability && silicon_version == 1)) { >> + /* TJA1120/TJA1121 PHY configuration errata workaround. >> + * Apply PHY writes sequence before link up. >> + */ >> + if (!macsec_ability) { >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x4b95); >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0xf3cd); >> + } else { >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x89c7); >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0893); >> + } >> + >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0476, 0x58a0); >> + >> + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x8921, 0xa3a); >> + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x89F1, 0x16c1); >> + >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0); >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0); > > Please add macro with meaningful names for all the magic numbers used > above, thanks! > > Paolo > Hello, these registers are not documented in the datasheet or errata sheet. The access sequence comes 1-to-1 from the errata so I couldn't use macros. Regards, Andrei B. ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH net v2 1/2] net: phy: nxp-c45-tja11xx: add TJA112X PHY configuration errata 2025-03-06 12:03 ` Andrei Botila @ 2025-03-06 15:35 ` Andrew Lunn 2025-03-07 13:24 ` Simon Horman 0 siblings, 1 reply; 7+ messages in thread From: Andrew Lunn @ 2025-03-06 15:35 UTC (permalink / raw) To: Andrei Botila Cc: Paolo Abeni, Heiner Kallweit, Russell King, David S. Miller, Eric Dumazet, Jakub Kicinski, netdev, linux-kernel, s32, Christophe Lizzi, Alberto Ruiz, Enric Balletbo, stable > >> +/* Errata: ES_TJA1120 and ES_TJA1121 Rev. 1.0 — 28 November 2024 Section 3.1 */ > >> +static void nxp_c45_tja1120_errata(struct phy_device *phydev) > >> +{ > >> + int silicon_version, sample_type; > >> + bool macsec_ability; > >> + int phy_abilities; > >> + int ret = 0; > >> + > >> + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_ID3); > >> + if (ret < 0) > >> + return; > >> + > >> + sample_type = FIELD_GET(TJA1120_DEV_ID3_SAMPLE_TYPE, ret); > >> + if (sample_type != DEVICE_ID3_SAMPLE_TYPE_R) > >> + return; > >> + > >> + silicon_version = FIELD_GET(TJA1120_DEV_ID3_SILICON_VERSION, ret); > >> + > >> + phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1, > >> + VEND1_PORT_ABILITIES); > >> + macsec_ability = !!(phy_abilities & MACSEC_ABILITY); > >> + if ((!macsec_ability && silicon_version == 2) || > >> + (macsec_ability && silicon_version == 1)) { > >> + /* TJA1120/TJA1121 PHY configuration errata workaround. > >> + * Apply PHY writes sequence before link up. > >> + */ > >> + if (!macsec_ability) { > >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x4b95); > >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0xf3cd); > >> + } else { > >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x89c7); > >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0893); > >> + } > >> + > >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0476, 0x58a0); > >> + > >> + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x8921, 0xa3a); > >> + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x89F1, 0x16c1); > >> + > >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0); > >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0); > > > > Please add macro with meaningful names for all the magic numbers used > > above, thanks! > > > > Paolo > > > > Hello, these registers are not documented in the datasheet or errata sheet. > The access sequence comes 1-to-1 from the errata so I couldn't use macros. Yes, we sometimes just have to accept the drivers are doing magic we have no idea about because the vendor does not want to tell is. All the registers in MDIO_MMD_VEND1 are clearly vendor specific. The MDIO_MMD_PMAPMD registers are also in the range reserved for vendors. So i think we just have to accept it. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH net v2 1/2] net: phy: nxp-c45-tja11xx: add TJA112X PHY configuration errata 2025-03-06 15:35 ` Andrew Lunn @ 2025-03-07 13:24 ` Simon Horman 0 siblings, 0 replies; 7+ messages in thread From: Simon Horman @ 2025-03-07 13:24 UTC (permalink / raw) To: Andrew Lunn Cc: Andrei Botila, Paolo Abeni, Heiner Kallweit, Russell King, David S. Miller, Eric Dumazet, Jakub Kicinski, netdev, linux-kernel, s32, Christophe Lizzi, Alberto Ruiz, Enric Balletbo, stable On Thu, Mar 06, 2025 at 04:35:12PM +0100, Andrew Lunn wrote: > > >> +/* Errata: ES_TJA1120 and ES_TJA1121 Rev. 1.0 — 28 November 2024 Section 3.1 */ > > >> +static void nxp_c45_tja1120_errata(struct phy_device *phydev) > > >> +{ > > >> + int silicon_version, sample_type; > > >> + bool macsec_ability; > > >> + int phy_abilities; > > >> + int ret = 0; > > >> + > > >> + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_ID3); > > >> + if (ret < 0) > > >> + return; > > >> + > > >> + sample_type = FIELD_GET(TJA1120_DEV_ID3_SAMPLE_TYPE, ret); > > >> + if (sample_type != DEVICE_ID3_SAMPLE_TYPE_R) > > >> + return; > > >> + > > >> + silicon_version = FIELD_GET(TJA1120_DEV_ID3_SILICON_VERSION, ret); > > >> + > > >> + phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1, > > >> + VEND1_PORT_ABILITIES); > > >> + macsec_ability = !!(phy_abilities & MACSEC_ABILITY); > > >> + if ((!macsec_ability && silicon_version == 2) || > > >> + (macsec_ability && silicon_version == 1)) { > > >> + /* TJA1120/TJA1121 PHY configuration errata workaround. > > >> + * Apply PHY writes sequence before link up. > > >> + */ > > >> + if (!macsec_ability) { > > >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x4b95); > > >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0xf3cd); > > >> + } else { > > >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x89c7); > > >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0893); > > >> + } > > >> + > > >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0476, 0x58a0); > > >> + > > >> + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x8921, 0xa3a); > > >> + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x89F1, 0x16c1); > > >> + > > >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0); > > >> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0); > > > > > > Please add macro with meaningful names for all the magic numbers used > > > above, thanks! > > > > > > Paolo > > > > > > > Hello, these registers are not documented in the datasheet or errata sheet. > > The access sequence comes 1-to-1 from the errata so I couldn't use macros. > > Yes, we sometimes just have to accept the drivers are doing magic we > have no idea about because the vendor does not want to tell is. All > the registers in MDIO_MMD_VEND1 are clearly vendor specific. The > MDIO_MMD_PMAPMD registers are also in the range reserved for > vendors. So i think we just have to accept it. +1 It can happen that vendors regard such information as IP that they do not wish to disclose. Not saying that is the case here. Just saying it is one reason that we sometimes have to accept such things. So I think what you say above is completely reasonable. > Reviewed-by: Andrew Lunn <andrew@lunn.ch> > > Andrew > ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH net v2 2/2] net: phy: nxp-c45-tja11xx: add TJA112XB SGMII PCS restart errata [not found] <20250304160619.181046-1-andrei.botila@oss.nxp.com> 2025-03-04 16:06 ` [PATCH net v2 1/2] net: phy: nxp-c45-tja11xx: add TJA112X PHY configuration errata Andrei Botila @ 2025-03-04 16:06 ` Andrei Botila 1 sibling, 0 replies; 7+ messages in thread From: Andrei Botila @ 2025-03-04 16:06 UTC (permalink / raw) To: Andrew Lunn, Heiner Kallweit, Russell King, David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni Cc: netdev, linux-kernel, s32, Christophe Lizzi, Alberto Ruiz, Enric Balletbo, Andrei Botila, stable TJA1120B/TJA1121B can achieve a stable operation of SGMII after a startup event by putting the SGMII PCS into power down mode and restart afterwards. It is necessary to put the SGMII PCS into power down mode and back up. Cc: stable@vger.kernel.org Fixes: f1fe5dff2b8a ("net: phy: nxp-c45-tja11xx: add TJA1120 support") Signed-off-by: Andrei Botila <andrei.botila@oss.nxp.com> --- drivers/net/phy/nxp-c45-tja11xx.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c index 709d6c9f7cba..e9fc54517449 100644 --- a/drivers/net/phy/nxp-c45-tja11xx.c +++ b/drivers/net/phy/nxp-c45-tja11xx.c @@ -114,6 +114,9 @@ #define MII_BASIC_CONFIG_RMII 0x5 #define MII_BASIC_CONFIG_MII 0x4 +#define VEND1_SGMII_BASIC_CONTROL 0xB000 +#define SGMII_LPM BIT(11) + #define VEND1_SYMBOL_ERROR_CNT_XTD 0x8351 #define EXTENDED_CNT_EN BIT(15) #define VEND1_MONITOR_STATUS 0xAC80 @@ -1598,11 +1601,11 @@ static int nxp_c45_set_phy_mode(struct phy_device *phydev) return 0; } -/* Errata: ES_TJA1120 and ES_TJA1121 Rev. 1.0 — 28 November 2024 Section 3.1 */ +/* Errata: ES_TJA1120 and ES_TJA1121 Rev. 1.0 — 28 November 2024 Section 3.1 & 3.2 */ static void nxp_c45_tja1120_errata(struct phy_device *phydev) { + bool macsec_ability, sgmii_ability; int silicon_version, sample_type; - bool macsec_ability; int phy_abilities; int ret = 0; @@ -1619,6 +1622,7 @@ static void nxp_c45_tja1120_errata(struct phy_device *phydev) phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_ABILITIES); macsec_ability = !!(phy_abilities & MACSEC_ABILITY); + sgmii_ability = !!(phy_abilities & SGMII_ABILITY); if ((!macsec_ability && silicon_version == 2) || (macsec_ability && silicon_version == 1)) { /* TJA1120/TJA1121 PHY configuration errata workaround. @@ -1639,6 +1643,18 @@ static void nxp_c45_tja1120_errata(struct phy_device *phydev) phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0); phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0); + + if (sgmii_ability) { + /* TJA1120B/TJA1121B SGMII PCS restart errata workaround. + * Put SGMII PCS into power down mode and back up. + */ + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, + VEND1_SGMII_BASIC_CONTROL, + SGMII_LPM); + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, + VEND1_SGMII_BASIC_CONTROL, + SGMII_LPM); + } } } -- 2.48.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
[parent not found: <20250304160402.180548-1-andrei.botila@oss.nxp.com>]
* [PATCH net v2 1/2] net: phy: nxp-c45-tja11xx: add TJA112X PHY configuration errata [not found] <20250304160402.180548-1-andrei.botila@oss.nxp.com> @ 2025-03-04 16:04 ` Andrei Botila 0 siblings, 0 replies; 7+ messages in thread From: Andrei Botila @ 2025-03-04 16:04 UTC (permalink / raw) To: andrei.botila; +Cc: Andrei Botila, stable The most recent sillicon versions of TJA1120 and TJA1121 can achieve full silicon performance by putting the PHY in managed mode. It is necessary to apply these PHY writes before link gets established. Application of this fix is required after restart of device and wakeup from sleep. Cc: stable@vger.kernel.org Fixes: f1fe5dff2b8a ("net: phy: nxp-c45-tja11xx: add TJA1120 support") Signed-off-by: Andrei Botila <andrei.botila@oss.nxp.com> --- drivers/net/phy/nxp-c45-tja11xx.c | 52 +++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c index 34231b5b9175..709d6c9f7cba 100644 --- a/drivers/net/phy/nxp-c45-tja11xx.c +++ b/drivers/net/phy/nxp-c45-tja11xx.c @@ -22,6 +22,11 @@ #define PHY_ID_TJA_1103 0x001BB010 #define PHY_ID_TJA_1120 0x001BB031 +#define VEND1_DEVICE_ID3 0x0004 +#define TJA1120_DEV_ID3_SILICON_VERSION GENMASK(15, 12) +#define TJA1120_DEV_ID3_SAMPLE_TYPE GENMASK(11, 8) +#define DEVICE_ID3_SAMPLE_TYPE_R 0x9 + #define VEND1_DEVICE_CONTROL 0x0040 #define DEVICE_CONTROL_RESET BIT(15) #define DEVICE_CONTROL_CONFIG_GLOBAL_EN BIT(14) @@ -1593,6 +1598,50 @@ static int nxp_c45_set_phy_mode(struct phy_device *phydev) return 0; } +/* Errata: ES_TJA1120 and ES_TJA1121 Rev. 1.0 — 28 November 2024 Section 3.1 */ +static void nxp_c45_tja1120_errata(struct phy_device *phydev) +{ + int silicon_version, sample_type; + bool macsec_ability; + int phy_abilities; + int ret = 0; + + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_ID3); + if (ret < 0) + return; + + sample_type = FIELD_GET(TJA1120_DEV_ID3_SAMPLE_TYPE, ret); + if (sample_type != DEVICE_ID3_SAMPLE_TYPE_R) + return; + + silicon_version = FIELD_GET(TJA1120_DEV_ID3_SILICON_VERSION, ret); + + phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1, + VEND1_PORT_ABILITIES); + macsec_ability = !!(phy_abilities & MACSEC_ABILITY); + if ((!macsec_ability && silicon_version == 2) || + (macsec_ability && silicon_version == 1)) { + /* TJA1120/TJA1121 PHY configuration errata workaround. + * Apply PHY writes sequence before link up. + */ + if (!macsec_ability) { + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x4b95); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0xf3cd); + } else { + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x89c7); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0893); + } + + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0476, 0x58a0); + + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x8921, 0xa3a); + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x89F1, 0x16c1); + + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0); + } +} + static int nxp_c45_config_init(struct phy_device *phydev) { int ret; @@ -1609,6 +1658,9 @@ static int nxp_c45_config_init(struct phy_device *phydev) phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 1); phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 2); + if (phy_id_compare(phydev->phy_id, PHY_ID_TJA_1120, GENMASK(31, 4))) + nxp_c45_tja1120_errata(phydev); + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG, PHY_CONFIG_AUTO); -- 2.48.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-03-07 13:24 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
[not found] <20250304160619.181046-1-andrei.botila@oss.nxp.com>
2025-03-04 16:06 ` [PATCH net v2 1/2] net: phy: nxp-c45-tja11xx: add TJA112X PHY configuration errata Andrei Botila
2025-03-06 9:43 ` Paolo Abeni
2025-03-06 12:03 ` Andrei Botila
2025-03-06 15:35 ` Andrew Lunn
2025-03-07 13:24 ` Simon Horman
2025-03-04 16:06 ` [PATCH net v2 2/2] net: phy: nxp-c45-tja11xx: add TJA112XB SGMII PCS restart errata Andrei Botila
[not found] <20250304160402.180548-1-andrei.botila@oss.nxp.com>
2025-03-04 16:04 ` [PATCH net v2 1/2] net: phy: nxp-c45-tja11xx: add TJA112X PHY configuration errata Andrei Botila
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox