From: "Krzysztof Wilczyński" <kw@linux.com>
To: Siddharth Vadapalli <s-vadapalli@ti.com>
Cc: lpieralisi@kernel.org, vigneshr@ti.com,
manivannan.sadhasivam@linaro.org, robh@kernel.org,
bhelgaas@google.com, rogerq@kernel.org,
linux-omap@vger.kernel.org, linux-pci@vger.kernel.org,
stable@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, srk@ti.com
Subject: Re: [PATCH] PCI: j721e: Fix the value of linkdown_irq_regfield for J784S4
Date: Tue, 11 Mar 2025 06:07:46 +0900 [thread overview]
Message-ID: <20250310210746.GA2377483@rocinante> (raw)
In-Reply-To: <20250305132018.2260771-1-s-vadapalli@ti.com>
Hello,
> Hence, set 'linkdown_irq_regfield' to the macro 'J7200_LINK_DOWN' which
> expands to BIT(10) and was first defined for the J7200 SoC. Other SoCs
> already reuse this macro since it accurately represents the link-state
> field in their respective "PCIE_INTD_ENABLE_REG_SYS_2" register.
Can you confirm for me that the following use the correct macro?
333-static const struct j721e_pcie_data j721e_pcie_rc_data = {
337: .linkdown_irq_regfield = LINK_DOWN,
341-static const struct j721e_pcie_data j721e_pcie_ep_data = {
343: .linkdown_irq_regfield = LINK_DOWN,
347-static const struct j721e_pcie_data j7200_pcie_rc_data = {
350: .linkdown_irq_regfield = J7200_LINK_DOWN,
362-static const struct j721e_pcie_data am64_pcie_rc_data = {
364: .linkdown_irq_regfield = J7200_LINK_DOWN,
369-static const struct j721e_pcie_data am64_pcie_ep_data = {
371: .linkdown_irq_regfield = J7200_LINK_DOWN,
375-static const struct j721e_pcie_data j784s4_pcie_rc_data = {
379: .linkdown_irq_regfield = LINK_DOWN,
383-static const struct j721e_pcie_data j784s4_pcie_ep_data = {
385: .linkdown_irq_regfield = LINK_DOWN,
389-static const struct j721e_pcie_data j722s_pcie_rc_data = {
391: .linkdown_irq_regfield = J7200_LINK_DOWN,
I am asking as some use LINK_DOWN, so I wanted to make sure.
Tht said, the following has no .linkdown_irq_regfield property set:
355-static const struct j721e_pcie_data j7200_pcie_ep_data = {
356- .mode = PCI_MODE_EP,
357- .quirk_detect_quiet_flag = true,
358- .quirk_disable_flr = true,
359- .max_lanes = 2,
360-};
Would this be a problem? Or is this as expected?
Thank you!
Krzysztof
next prev parent reply other threads:[~2025-03-10 21:07 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-05 13:20 [PATCH] PCI: j721e: Fix the value of linkdown_irq_regfield for J784S4 Siddharth Vadapalli
2025-03-10 21:07 ` Krzysztof Wilczyński [this message]
2025-03-11 5:18 ` Siddharth Vadapalli
2025-03-11 7:25 ` Krzysztof Wilczyński
2025-03-11 7:32 ` Siddharth Vadapalli
2025-03-11 15:21 ` Krzysztof Wilczyński
2025-03-11 15:29 ` Siddharth Vadapalli
2025-03-11 15:34 ` Krzysztof Wilczyński
2025-03-11 15:00 ` Krzysztof Wilczyński
2025-03-12 16:16 ` Bjorn Helgaas
2025-03-13 5:55 ` Siddharth Vadapalli
2025-03-13 16:02 ` Bjorn Helgaas
2025-03-14 4:17 ` Siddharth Vadapalli
2025-03-26 6:54 ` Krzysztof Wilczyński
2025-03-26 7:01 ` Siddharth Vadapalli
2025-03-26 7:08 ` Krzysztof Wilczyński
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