From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CCBA14BF89; Tue, 11 Mar 2025 15:31:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741707100; cv=none; b=OX+6nQ41diMz2yhzqQKz44QmBxO8CAPFxIRYAY5lq1utHNQAB8wPbzMV6mApjvpDRm4vpLyx4sYv/0rNusqR46LPpULbsikY9jJSJmZKlkYLoCwu2mcJK+jvomtuv/DHDK2zymp2dG8AiBkSkWnmT1vRibDdQlBhv+MyzXq0Jlo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741707100; c=relaxed/simple; bh=uSpb3pu4CsKMRiuobGfaBI+YbIxmJHgGw0Lyv+dwzJ4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PCmlNSEwTy7uLOtVNV0+Wte//CfXmQ3Ynt2F4RtRbXk/l0s4t5n3uaRWA0F1tveGYyRzZoV6hBjgwjsWlfiFQgtF2OJ5OAFI3oWHYKD+lKm6X7kQUagk+PVAN1bpreJKusW0hKxmox+eSzMoYvg+HO1lNi6O6I1v96xcdvkn5fU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=mWT2jsgb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="mWT2jsgb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6794FC4CEE9; Tue, 11 Mar 2025 15:31:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1741707099; bh=uSpb3pu4CsKMRiuobGfaBI+YbIxmJHgGw0Lyv+dwzJ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mWT2jsgbo3ZeP4L24P2czjXxOO4r+I47KNmZKcH4UpakJY5r0H6IjICctzlRVMSLj oWT4vWS+j9kgvG2N90Bh1mHYQQzy61H5mS/y1nQ41HIa5FSyXu3vj+6oD8Vl+w9We8 FGnqerILfJhh4KwIdWTNYC4JXsc+jM6pS4dt0tJY= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Maxim Levitsky , Sean Christopherson , "Peter Zijlstra (Intel)" Subject: [PATCH 5.10 246/462] perf/x86/intel: Ensure LBRs are disabled when a CPU is starting Date: Tue, 11 Mar 2025 15:58:32 +0100 Message-ID: <20250311145808.082529582@linuxfoundation.org> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250311145758.343076290@linuxfoundation.org> References: <20250311145758.343076290@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.10-stable review patch. If anyone has any objections, please let me know. ------------------ From: Sean Christopherson commit c631a2de7ae48d50434bdc205d901423f8577c65 upstream. Explicitly clear DEBUGCTL.LBR when a CPU is starting, prior to purging the LBR MSRs themselves, as at least one system has been found to transfer control to the kernel with LBRs enabled (it's unclear whether it's a BIOS flaw or a CPU goof). Because the kernel preserves the original DEBUGCTL, even when toggling LBRs, leaving DEBUGCTL.LBR as is results in running with LBRs enabled at all times. Closes: https://lore.kernel.org/all/c9d8269bff69f6359731d758e3b1135dedd7cc61.camel@redhat.com Reported-by: Maxim Levitsky Signed-off-by: Sean Christopherson Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Maxim Levitsky Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20250131010721.470503-1-seanjc@google.com Signed-off-by: Greg Kroah-Hartman --- arch/x86/events/intel/core.c | 5 ++++- arch/x86/include/asm/msr-index.h | 3 ++- 2 files changed, 6 insertions(+), 2 deletions(-) --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4078,8 +4078,11 @@ static void intel_pmu_cpu_starting(int c init_debug_store_on_cpu(cpu); /* - * Deal with CPUs that don't clear their LBRs on power-up. + * Deal with CPUs that don't clear their LBRs on power-up, and that may + * even boot with LBRs enabled. */ + if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && x86_pmu.lbr_nr) + msr_clear_bit(MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_LBR_BIT); intel_pmu_lbr_reset(); cpuc->lbr_sel = NULL; --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -326,7 +326,8 @@ #define MSR_IA32_PASID_VALID BIT_ULL(31) /* DEBUGCTLMSR bits (others vary by model): */ -#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ +#define DEBUGCTLMSR_LBR_BIT 0 /* last branch recording */ +#define DEBUGCTLMSR_LBR (1UL << DEBUGCTLMSR_LBR_BIT) #define DEBUGCTLMSR_BTF_SHIFT 1 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ #define DEBUGCTLMSR_TR (1UL << 6)