From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54B8922A4F4; Mon, 7 Apr 2025 18:13:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744049592; cv=none; b=N9fmUmMfo1WBxC219q0OSNCtR2XG/781wvuPkA9c9qbif8DjHEaah2awgz9JmIVHXqR1S+RiUZ8SLPEqV5cjPcvwFcoiFO5ly9PTkDWPs96BAnlH6C1Rj2mHKltpk/bk5R9OkdGk9yBYEYSRogViX3f3MtzL+yq2M6/1KAZH8p8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744049592; c=relaxed/simple; bh=bXaaG1N/AIxufZ9GI9/+KsnLYgzJNlInmR5Z0xcBVJ0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=n/NmDVrBQPG1RST0YjbKE4GIZS3EGR38BTVq1LtIuIqBD/lH53KgqEWVVg6/oWotyGHt+tsivWo0Moyaj2fY1+32zqoPzNOpIWS3shba84n6zY/APDCAgALjUQA4/lRB9Q+QJwMvfYL3kl/h1ji7MZ+EGLLlxz2GbE0WXCNxt/o= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hfIp5E2R; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hfIp5E2R" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F0C32C4CEDD; Mon, 7 Apr 2025 18:13:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744049591; bh=bXaaG1N/AIxufZ9GI9/+KsnLYgzJNlInmR5Z0xcBVJ0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hfIp5E2ROssoyfNUlDMntdWU4L6zvLInV+RLBQ1imCZhP+x6ZOCgKV5Rpb7clllxk Aec9T9dnkGLvo5G6N4Gd1nQ7PCe/YRPB9owRUn3zjEJw6+DRtPD4LuoljAUCbMLX1Y RvzgZ/7Lw234QnpHtP/Dqs0C3a3d6WDpcvdNnBPuUOir+mlz7ZbtVgXISVscNDmASJ GHlzfSEudMfXHlMg6ngibAOmYTbCm3CuUFeMvbPB+/beAvB2mG0cBXAjEKsXSyl3YW wWLAh84qidOPtU6J8Z72nzXPmR+PZhemhNkC9gUTN7yQyUPxKJ1ssguQuOMqI5+/w7 IiIl0FzcDpx3A== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Nicolin Chen , Jason Gunthorpe , Pranjal Shrivastava , Will Deacon , Sasha Levin , joro@8bytes.org, jgg@ziepe.ca, kevin.tian@intel.com, ddutile@redhat.com, nathan@kernel.org, peterz@infradead.org, yi.l.liu@intel.com, jsnitsel@redhat.com, mshavit@google.com, zhangzekun11@huawei.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev Subject: [PATCH AUTOSEL 6.13 21/28] iommu/arm-smmu-v3: Set MEV bit in nested STE for DoS mitigations Date: Mon, 7 Apr 2025 14:12:11 -0400 Message-Id: <20250407181224.3180941-21-sashal@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250407181224.3180941-1-sashal@kernel.org> References: <20250407181224.3180941-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.13.10 Content-Transfer-Encoding: 8bit From: Nicolin Chen [ Upstream commit da0c56520e880441d0503d0cf0d6853dcfb5f1a4 ] There is a DoS concern on the shared hardware event queue among devices passed through to VMs, that too many translation failures that belong to VMs could overflow the shared hardware event queue if those VMs or their VMMs don't handle/recover the devices properly. The MEV bit in the STE allows to configure the SMMU HW to merge similar event records, though there is no guarantee. Set it in a nested STE for DoS mitigations. In the future, we might want to enable the MEV for non-nested cases too such as domain->type == IOMMU_DOMAIN_UNMANAGED or even IOMMU_DOMAIN_DMA. Link: https://patch.msgid.link/r/8ed12feef67fc65273d0f5925f401a81f56acebe.1741719725.git.nicolinc@nvidia.com Reviewed-by: Jason Gunthorpe Reviewed-by: Pranjal Shrivastava Acked-by: Will Deacon Signed-off-by: Nicolin Chen Signed-off-by: Jason Gunthorpe Signed-off-by: Sasha Levin --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 2 ++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 4 ++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index c7cc613050d93..6d94c9fc08289 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -43,6 +43,8 @@ static void arm_smmu_make_nested_cd_table_ste( target->data[0] |= nested_domain->ste[0] & ~cpu_to_le64(STRTAB_STE_0_CFG); target->data[1] |= nested_domain->ste[1]; + /* Merge events for DoS mitigations on eventq */ + target->data[1] |= cpu_to_le64(STRTAB_STE_1_MEV); } /* diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 42a89d499cda8..b7c5971da8b94 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1031,7 +1031,7 @@ void arm_smmu_get_ste_used(const __le64 *ent, __le64 *used_bits) cpu_to_le64(STRTAB_STE_1_S1DSS | STRTAB_STE_1_S1CIR | STRTAB_STE_1_S1COR | STRTAB_STE_1_S1CSH | STRTAB_STE_1_S1STALLD | STRTAB_STE_1_STRW | - STRTAB_STE_1_EATS); + STRTAB_STE_1_EATS | STRTAB_STE_1_MEV); used_bits[2] |= cpu_to_le64(STRTAB_STE_2_S2VMID); /* @@ -1047,7 +1047,7 @@ void arm_smmu_get_ste_used(const __le64 *ent, __le64 *used_bits) if (cfg & BIT(1)) { used_bits[1] |= cpu_to_le64(STRTAB_STE_1_S2FWB | STRTAB_STE_1_EATS | - STRTAB_STE_1_SHCFG); + STRTAB_STE_1_SHCFG | STRTAB_STE_1_MEV); used_bits[2] |= cpu_to_le64(STRTAB_STE_2_S2VMID | STRTAB_STE_2_VTCR | STRTAB_STE_2_S2AA64 | STRTAB_STE_2_S2ENDI | diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 0107d3f333a1c..73cc56ff11db7 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -266,6 +266,7 @@ static inline u32 arm_smmu_strtab_l2_idx(u32 sid) #define STRTAB_STE_1_S1COR GENMASK_ULL(5, 4) #define STRTAB_STE_1_S1CSH GENMASK_ULL(7, 6) +#define STRTAB_STE_1_MEV (1UL << 19) #define STRTAB_STE_1_S2FWB (1UL << 25) #define STRTAB_STE_1_S1STALLD (1UL << 27) -- 2.39.5