From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 735E922171B; Mon, 7 Apr 2025 18:12:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744049563; cv=none; b=UtgYJ58W3LL8eOuWJi+VoTbsWa8zYL9rscIh+9shmm1OHy2TDYHOX4ugubNPHXkqEl0BVcfpcpeqbQpBKfhIo5B54nk2vAbVzeHGdUHlVEdju5njp0BiBZzDwu+gbFn00/z2i0Amvk/mwRLLmhopi+xuVCbUrt0VIPtaWz22OiU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744049563; c=relaxed/simple; bh=P9IARbyBPJ3Osu5SDwsFJok3oD6DIO0uGCgbsgkHuDE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=CITkXrptERYF0Sb+hpLUfBge0w6D8laOhSBHFGJFsgsKlNKfKAZaNa5IujTnnhxgOyCldubK0P+K7EkBPrky6r4sFzLUbqHnfho5slob7DQX5QUD9k+FLfeYrtyPgZwHdDZxPum4C7quE9IiddeqtvYD9Cn2X6mfbHdPDxdpYdg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=t9sFWmNW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="t9sFWmNW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0E6F5C4CEE9; Mon, 7 Apr 2025 18:12:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744049562; bh=P9IARbyBPJ3Osu5SDwsFJok3oD6DIO0uGCgbsgkHuDE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=t9sFWmNWnG23zx1PKNh6fcXE8ujNBQFkuphbWnx3BMvUwewJHMj6Pp8Hxw8IZ9u52 NM5gDEtC4senKb/JyQZqeP/OK723EkY4m6+b2s/LJATgtVJGPqwn0sX0kpqpPs9I2V qLQ2+wWsElrUk072t3FV7Cmkl0/UMu2ikKMessFwMaPbib4rmI4wJrWf7paRqbThhA Ms1wwF7OQm9QrA8pUb080lrHEijXvDCHSKx0dCip6beK0lmHpEWHkS6EjFB0qqdUSS nT4OTOj8cThNAxtcCngQpPsVOmA8UmeD9nKGO306AOkCDfEuVGz1Q8V8pLjHnWs1lg tjaCDeubAcwsQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Andy Shevchenko , Ferry Toth , Thinh Nguyen , Greg Kroah-Hartman , Sasha Levin , linux-usb@vger.kernel.org Subject: [PATCH AUTOSEL 6.13 08/28] usb: dwc3: gadget: Avoid using reserved endpoints on Intel Merrifield Date: Mon, 7 Apr 2025 14:11:58 -0400 Message-Id: <20250407181224.3180941-8-sashal@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250407181224.3180941-1-sashal@kernel.org> References: <20250407181224.3180941-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.13.10 Content-Transfer-Encoding: 8bit From: Andy Shevchenko [ Upstream commit 461f24bff86808ee5fbfe74751a825f8a7ab24e0 ] Intel Merrifield SoC uses these endpoints for tracing and they cannot be re-allocated if being used because the side band flow control signals are hard wired to certain endpoints: • 1 High BW Bulk IN (IN#1) (RTIT) • 1 1KB BW Bulk IN (IN#8) + 1 1KB BW Bulk OUT (Run Control) (OUT#8) In device mode, since RTIT (EP#1) and EXI/RunControl (EP#8) uses External Buffer Control (EBC) mode, these endpoints are to be mapped to EBC mode (to be done by EXI target driver). Additionally TRB for RTIT and EXI are maintained in STM (System Trace Module) unit and the EXI target driver will as well configure the TRB location for EP #1 IN and EP#8 (IN and OUT). Since STM/PTI and EXI hardware blocks manage these endpoints and interface to OTG3 controller through EBC interface, there is no need to enable any events (such as XferComplete etc) for these end points. Signed-off-by: Andy Shevchenko Tested-by: Ferry Toth Acked-by: Thinh Nguyen Link: https://lore.kernel.org/r/20250212193116.2487289-5-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/usb/dwc3/dwc3-pci.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c index 052852f801467..54a4ee2b90b7f 100644 --- a/drivers/usb/dwc3/dwc3-pci.c +++ b/drivers/usb/dwc3/dwc3-pci.c @@ -148,11 +148,21 @@ static const struct property_entry dwc3_pci_intel_byt_properties[] = { {} }; +/* + * Intel Merrifield SoC uses these endpoints for tracing and they cannot + * be re-allocated if being used because the side band flow control signals + * are hard wired to certain endpoints: + * - 1 High BW Bulk IN (IN#1) (RTIT) + * - 1 1KB BW Bulk IN (IN#8) + 1 1KB BW Bulk OUT (Run Control) (OUT#8) + */ +static const u8 dwc3_pci_mrfld_reserved_endpoints[] = { 3, 16, 17 }; + static const struct property_entry dwc3_pci_mrfld_properties[] = { PROPERTY_ENTRY_STRING("dr_mode", "otg"), PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"), PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), + PROPERTY_ENTRY_U8_ARRAY("snps,reserved-endpoints", dwc3_pci_mrfld_reserved_endpoints), PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"), PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), {} -- 2.39.5