From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8BAD2F22E5; Mon, 5 May 2025 23:13:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746486787; cv=none; b=D6bwFSU7OgT2Kip6X62+9c+uVze4Y1dfdjFTy+gh+GIN0BrqFcpyuiRQEzWcbTDtXzTtfaFbRvwCtKiZz1e4MYhFbuYNUVJZPNzz1t49JOZz661mHZD496yvmdesR86NNydtCLg3fQHYWCzeETrH0dM+KDUuvPqFv3nMnR1L6EQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746486787; c=relaxed/simple; bh=Ky2YJCmBq4yjzjzdNAXmiq5hU2l7Onct2vzG80Vm9Xk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hZWHt1Y+U7xx0eCZji0NbL4wgUhQelIpNlR7Bh1338gGSsjfkA8RvnZ1P9KJkmxF6VLwcrhWFMwj4KmL8tKYveMlish98rRZgA+pbX8YoapJTylKzpKRYHG6yX8LueuVDwqMOMoSR33Py/h+/7P0+ocjl/mgkLtpgy0HKjjCg9c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Y8Kx0bom; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Y8Kx0bom" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7451AC4CEED; Mon, 5 May 2025 23:13:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746486785; bh=Ky2YJCmBq4yjzjzdNAXmiq5hU2l7Onct2vzG80Vm9Xk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y8Kx0bom/lb2bIX51cOtRkGuMeBRqzeGnGM5e0C9ET/IHcKV0MJrEbfmGLiC3cCW9 CBpu+WgdgYHL+DO96NouMOrsJDTFKqZUfAbJO981ZnAoAje/iZM6i+PGrdpcChfVmL rUJQHG5uXjXce9QjaG8muWNCUkQGQxy128pf645Ru3hSiBAVPOiOrwLJx4sHmzVzxP 4RfYmPrDPjYCheR1n0PVSZPZeq0zwlJdaq2AY+VxwswlrStf1rp5FHLODX6M/DM9jz BpgYmnUDUYE0M7zQnvTav1PxHrMKo0qS5aNf8Cyh4NPyp7H679K7R5nTHOD/5dRFSQ aufu1ZYrd+swQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Ravi Bangoria , Peter Zijlstra , Namhyung Kim , Sasha Levin , mingo@redhat.com, acme@kernel.org, tglx@linutronix.de, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, linux-perf-users@vger.kernel.org Subject: [PATCH AUTOSEL 6.1 203/212] perf/amd/ibs: Fix perf_ibs_op.cnt_mask for CurCnt Date: Mon, 5 May 2025 19:06:15 -0400 Message-Id: <20250505230624.2692522-203-sashal@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250505230624.2692522-1-sashal@kernel.org> References: <20250505230624.2692522-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.1.136 Content-Transfer-Encoding: 8bit From: Ravi Bangoria [ Upstream commit 46dcf85566170d4528b842bf83ffc350d71771fa ] IBS Op uses two counters: MaxCnt and CurCnt. MaxCnt is programmed with the desired sample period. IBS hw generates sample when CurCnt reaches to MaxCnt. The size of these counter used to be 20 bits but later they were extended to 27 bits. The 7 bit extension is indicated by CPUID Fn8000_001B_EAX[6 / OpCntExt]. perf_ibs->cnt_mask variable contains bit masks for MaxCnt and CurCnt. But IBS driver does not set upper 7 bits of CurCnt in cnt_mask even when OpCntExt CPUID bit is set. Fix this. IBS driver uses cnt_mask[CurCnt] bits only while disabling an event. Fortunately, CurCnt bits are not read from MSR while re-enabling the event, instead MaxCnt is programmed with desired period and CurCnt is set to 0. Hence, we did not see any issues so far. Signed-off-by: Ravi Bangoria Signed-off-by: Peter Zijlstra (Intel) Acked-by: Namhyung Kim Link: https://lkml.kernel.org/r/20250115054438.1021-5-ravi.bangoria@amd.com Signed-off-by: Sasha Levin --- arch/x86/events/amd/ibs.c | 3 ++- arch/x86/include/asm/perf_event.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 37cbbc5c659a5..8c385e231e070 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1216,7 +1216,8 @@ static __init int perf_ibs_op_init(void) if (ibs_caps & IBS_CAPS_OPCNTEXT) { perf_ibs_op.max_period |= IBS_OP_MAX_CNT_EXT_MASK; perf_ibs_op.config_mask |= IBS_OP_MAX_CNT_EXT_MASK; - perf_ibs_op.cnt_mask |= IBS_OP_MAX_CNT_EXT_MASK; + perf_ibs_op.cnt_mask |= (IBS_OP_MAX_CNT_EXT_MASK | + IBS_OP_CUR_CNT_EXT_MASK); } if (ibs_caps & IBS_CAPS_ZEN4) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 4d810b9478a43..fa3576ef19daa 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -456,6 +456,7 @@ struct pebs_xmm { */ #define IBS_OP_CUR_CNT (0xFFF80ULL<<32) #define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32) +#define IBS_OP_CUR_CNT_EXT_MASK (0x7FULL<<52) #define IBS_OP_CNT_CTL (1ULL<<19) #define IBS_OP_VAL (1ULL<<18) #define IBS_OP_ENABLE (1ULL<<17) -- 2.39.5