Re: [PATCH] ACPI/PPTT: fix off-by-one error

["Heyne, Maximilian" <mheyne@amazon.de>]

On Wed, May 07, 2025 at 01:30:53PM +0100, Sudeep Holla wrote:
> On Wed, May 07, 2025 at 11:56:48AM +0000, Heyne, Maximilian wrote:
> > On Wed, May 07, 2025 at 12:52:18PM +0100, Sudeep Holla wrote:
> > > 
> > > Just to understand, this node is absolutely processor node with no
> > > private resources ? I find it hard to trust this as most of the CPUs
> > > do have L1 I&D caches. If they were present the table can't abruptly end
> > > like this.
> > 
> > Yes looks like it. In our case the ACPI subtable has length 0x14 which is
> > exactly sizeof(acpi_pptt_processor).
> > 
> 
> OK, this seem like it is emulated platform with no private resources as
> it is specified in the other similar patch clearly(QEMU/VM). So this
> doesn't match real platforms. Your PPTT is wrong if it is real hardware
> platform as you must have private resources.
> 
> Anyways if we allow emulation to present CPUs without private resources
> we may have to consider allowing this as the computed pointer will match
> the table end.

Is there a need by the ACPI specification that the Cache information
must come after the processor information? Because on our platform there
is Cache and it's described but at a different location seemingly. It
looks like caches are described first and then the CPUs.

I can try to drill even deeper here if you insist. As said I'm no
subject matter expert here. But is there something obviously wrong with
my patch or would it be ok to just take it?



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