From: Sasha Levin <sashal@kernel.org>
To: stable@vger.kernel.org
Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>,
Sasha Levin <sashal@kernel.org>
Subject: Re: [PATCH 5.15 v2 13/14] x86/its: Align RETs in BHB clear sequence to avoid thunking
Date: Wed, 14 May 2025 16:13:37 -0400 [thread overview]
Message-ID: <20250514113946-23aea5f5b7d675ec@stable.kernel.org> (raw)
In-Reply-To: <20250513-its-5-15-v2-13-90690efdc7e0@linux.intel.com>
[ Sasha's backport helper bot ]
Hi,
✅ All tests passed successfully. No issues detected.
No action required from the submitter.
The upstream commit SHA1 provided is correct: f0cd7091cc5a032c8870b4285305d9172569d126
Status in newer kernel trees:
6.14.y | Present (different SHA1: 375fe8890b23)
6.12.y | Present (different SHA1: 5eaa60e1baf1)
6.6.y | Present (different SHA1: f17249f8a872)
6.1.y | Present (different SHA1: 724e897203bd)
Note: The patch differs from the upstream commit:
---
1: f0cd7091cc5a0 ! 1: 9b2b6206dceda x86/its: Align RETs in BHB clear sequence to avoid thunking
@@ Metadata
## Commit message ##
x86/its: Align RETs in BHB clear sequence to avoid thunking
+ commit f0cd7091cc5a032c8870b4285305d9172569d126 upstream.
+
The software mitigation for BHI is to execute BHB clear sequence at syscall
entry, and possibly after a cBPF program. ITS mitigation thunks RETs in the
lower half of the cacheline. This causes the RETs in the BHB clear sequence
@@ arch/x86/entry/entry_64.S: SYM_CODE_END(rewind_stack_and_make_dead)
+ * Target Selection, rather than taking the slowpath via its_return_thunk.
*/
SYM_FUNC_START(clear_bhb_loop)
- ANNOTATE_NOENDBR
+ push %rbp
@@ arch/x86/entry/entry_64.S: SYM_FUNC_START(clear_bhb_loop)
call 1f
jmp 5f
---
Results of testing on various branches:
| Branch | Patch Apply | Build Test |
|---------------------------|-------------|------------|
| stable/linux-6.1.y | Success | Success |
next prev parent reply other threads:[~2025-05-14 20:13 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-14 6:06 [PATCH 5.15 v2 00/14] ITS mitigation Pawan Gupta
2025-05-14 6:06 ` [PATCH 5.15 v2 01/14] x86,nospec: Simplify {JMP,CALL}_NOSPEC Pawan Gupta
2025-05-14 20:13 ` Sasha Levin
2025-05-14 6:07 ` [PATCH 5.15 v2 02/14] x86/speculation: Simplify and make CALL_NOSPEC consistent Pawan Gupta
2025-05-14 20:14 ` Sasha Levin
2025-05-14 6:07 ` [PATCH 5.15 v2 03/14] x86/speculation: Add a conditional CS prefix to CALL_NOSPEC Pawan Gupta
2025-05-14 20:14 ` Sasha Levin
2025-05-14 6:07 ` [PATCH 5.15 v2 04/14] x86/speculation: Remove the extra #ifdef around CALL_NOSPEC Pawan Gupta
2025-05-14 20:13 ` Sasha Levin
2025-05-14 6:07 ` [PATCH 5.15 v2 05/14] Documentation: x86/bugs/its: Add ITS documentation Pawan Gupta
2025-05-14 20:14 ` Sasha Levin
2025-05-14 6:08 ` [PATCH 5.15 v2 06/14] x86/its: Enumerate Indirect Target Selection (ITS) bug Pawan Gupta
2025-05-14 20:13 ` Sasha Levin
2025-05-14 6:08 ` [PATCH 5.15 v2 07/14] x86/its: Add support for ITS-safe indirect thunk Pawan Gupta
2025-05-14 20:14 ` Sasha Levin
2025-05-14 6:08 ` [PATCH 5.15 v2 08/14] x86/alternative: Optimize returns patching Pawan Gupta
2025-05-14 20:14 ` Sasha Levin
2025-05-14 6:08 ` [PATCH 5.15 v2 09/14] x86/alternatives: Remove faulty optimization Pawan Gupta
2025-05-14 20:13 ` Sasha Levin
2025-05-14 6:09 ` [PATCH 5.15 v2 10/14] x86/its: Add support for ITS-safe return thunk Pawan Gupta
2025-05-14 20:13 ` Sasha Levin
2025-05-14 6:09 ` [PATCH 5.15 v2 11/14] x86/its: Enable Indirect Target Selection mitigation Pawan Gupta
2025-05-14 20:14 ` Sasha Levin
2025-05-14 6:09 ` [PATCH 5.15 v2 12/14] x86/its: Add "vmexit" option to skip mitigation on some CPUs Pawan Gupta
2025-05-14 20:14 ` Sasha Levin
2025-05-14 6:10 ` [PATCH 5.15 v2 13/14] x86/its: Align RETs in BHB clear sequence to avoid thunking Pawan Gupta
2025-05-14 20:13 ` Sasha Levin [this message]
2025-05-14 6:10 ` [PATCH 5.15 v2 14/14] x86/its: Use dynamic thunks for indirect branches Pawan Gupta
2025-05-14 20:14 ` Sasha Levin
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