From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B293217B425; Tue, 27 May 2025 17:02:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748365364; cv=none; b=YSgUxUimjeb27bt7RLmEHiKG6FuBN8s5esatlrTSU2zceJg0mzvEoPD01wjySzc1BI0M40LBp0jN+QLHFc8b86ix2s4Wn8TXBJUF96WPd0tnEzRFttLemD1SwBykB9Y46tuW2/rKaNXF9+rBcQnIhmUJk+BxUyUHBnjzSIMB6HM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748365364; c=relaxed/simple; bh=LsbLEdwkK/HYOeadJLf35wLvR09E45fSMFwc9QL6ECI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aM66Vb0x3RHj4Yn9c2T9z3adjO/0uiiLF0edwzciONa7z17jSgUEcCRglFAPJvqM1cu+MQqm20OsDnLLc7uQsl0NBayUU7eG3f021YEiyI9hY9445cFmN+CKYweHiSyHeKxBy1s71EO1jaA+srT8ZM8dtg+MjvHFpclvnZIMZ/U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=0YGxy09a; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="0YGxy09a" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1965FC4CEE9; Tue, 27 May 2025 17:02:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1748365364; bh=LsbLEdwkK/HYOeadJLf35wLvR09E45fSMFwc9QL6ECI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=0YGxy09a+21V+ZI/xjbxrY1vBEScQxpkl9ryLqnL5jOjqNtFVw5LDzM0eLYuSCS9l doc36TjU+/g+jiSSvctzy24m3pRSsOeAIv3aG07vNuO0xLNuW7X/9buQfQEYDHen2t n8yOsQ8kQW6KN9LMVgTyxJuWk5D1RUmTz1t8uU8I= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Shahar Shitrit , Tariq Toukan , Mateusz Polchlopek , Jakub Kicinski , Sasha Levin Subject: [PATCH 6.12 353/626] net/mlx5: Modify LSB bitmask in temperature event to include only the first bit Date: Tue, 27 May 2025 18:24:06 +0200 Message-ID: <20250527162459.362029815@linuxfoundation.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250527162445.028718347@linuxfoundation.org> References: <20250527162445.028718347@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Shahar Shitrit [ Upstream commit 633f16d7e07c129a36b882c05379e01ce5bdb542 ] In the sensor_count field of the MTEWE register, bits 1-62 are supported only for unmanaged switches, not for NICs, and bit 63 is reserved for internal use. To prevent confusing output that may include set bits that are not relevant to NIC sensors, we update the bitmask to retain only the first bit, which corresponds to the sensor ASIC. Signed-off-by: Shahar Shitrit Signed-off-by: Tariq Toukan Reviewed-by: Mateusz Polchlopek Link: https://patch.msgid.link/20250213094641.226501-4-tariqt@nvidia.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/mellanox/mlx5/core/events.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/events.c b/drivers/net/ethernet/mellanox/mlx5/core/events.c index d91ea53eb394d..cd8d107f7d9e3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/events.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/events.c @@ -163,6 +163,10 @@ static int temp_warn(struct notifier_block *nb, unsigned long type, void *data) u64 value_msb; value_lsb = be64_to_cpu(eqe->data.temp_warning.sensor_warning_lsb); + /* bit 1-63 are not supported for NICs, + * hence read only bit 0 (asic) from lsb. + */ + value_lsb &= 0x1; value_msb = be64_to_cpu(eqe->data.temp_warning.sensor_warning_msb); mlx5_core_warn(events->dev, -- 2.39.5