From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87C0D139579; Tue, 27 May 2025 17:10:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748365857; cv=none; b=Fx2Z21IakrvpfzFryxC9txywb4MmdSzLYMngbCf1fMQJNvCttm3DTmiGJ8ILdcrgDVJmj/FBFQVePLVMWDzKDOnG3tgXzEBIosth5BgV48wtG8kX6CqxdH0fsqApfMM1dsK4M/sfURSmt05+dZCYoGai0q5FDy/N92jV82ejFco= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748365857; c=relaxed/simple; bh=EnFoxBiW5ovyS0wCUzkIsc52VJYuMWDWrb+qpTqvdlU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=c4m0IGGxgb7kgCbJKDu0zI+n5yKinJq9V+6FFLAnu5Swqra4nqVs6XxalGHvA2CJHbZrnWgxs+C112dXkaIC+9WOeEmq6O+zXFChdLRwfKsC6i/czDqvbk1pFZUyhMmsQTAkQAk2dIn6T23MMxib0L+S01fty1VnMH2Wsm3C3C0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=N0n/NMJD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="N0n/NMJD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0FF67C4CEE9; Tue, 27 May 2025 17:10:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1748365857; bh=EnFoxBiW5ovyS0wCUzkIsc52VJYuMWDWrb+qpTqvdlU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N0n/NMJD6+K983I/YIzZvHV5IoSbyahgI6JaVBkubyxOghb25fwYg7ir+eUQ7lRBE VY2ZuaXb3NyNVGcET2Q/tXvSKxRPIM/U/zGMxaSyNe2qsOWkPVWAC1fCDYxTsHO7Zl 7bWndPMrANk16lC7Dt3gGBe3WHIVieMAbzugL93A= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Ravi Bangoria , "Peter Zijlstra (Intel)" , Namhyung Kim , Sasha Levin Subject: [PATCH 6.12 480/626] perf/amd/ibs: Fix ->config to sample period calculation for OP PMU Date: Tue, 27 May 2025 18:26:13 +0200 Message-ID: <20250527162504.491264667@linuxfoundation.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250527162445.028718347@linuxfoundation.org> References: <20250527162445.028718347@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Ravi Bangoria [ Upstream commit 598bdf4fefff5af4ce6d26d16f7b2a20808fc4cb ] Instead of using standard perf_event_attr->freq=0 and ->sample_period fields, IBS event in 'sample period mode' can also be opened by setting period value directly in perf_event_attr->config in a MaxCnt bit-field format. IBS OP MaxCnt bits are defined as: (high bits) IbsOpCtl[26:20] = IbsOpMaxCnt[26:20] (low bits) IbsOpCtl[15:0] = IbsOpMaxCnt[19:4] Perf event sample period can be derived from MaxCnt bits as: sample_period = (high bits) | ((low_bits) << 4); However, current code just masks MaxCnt bits and shifts all of them, including high bits, which is incorrect. Fix it. Signed-off-by: Ravi Bangoria Signed-off-by: Peter Zijlstra (Intel) Acked-by: Namhyung Kim Link: https://lkml.kernel.org/r/20250115054438.1021-4-ravi.bangoria@amd.com Signed-off-by: Sasha Levin --- arch/x86/events/amd/ibs.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 8f3b5764e139d..d34ee6f04f18f 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -272,7 +272,7 @@ static int perf_ibs_init(struct perf_event *event) { struct hw_perf_event *hwc = &event->hw; struct perf_ibs *perf_ibs; - u64 max_cnt, config; + u64 config; int ret; perf_ibs = get_ibs_pmu(event->attr.type); @@ -309,10 +309,19 @@ static int perf_ibs_init(struct perf_event *event) if (!hwc->sample_period) hwc->sample_period = 0x10; } else { - max_cnt = config & perf_ibs->cnt_mask; + u64 period = 0; + + if (perf_ibs == &perf_ibs_op) { + period = (config & IBS_OP_MAX_CNT) << 4; + if (ibs_caps & IBS_CAPS_OPCNTEXT) + period |= config & IBS_OP_MAX_CNT_EXT_MASK; + } else { + period = (config & IBS_FETCH_MAX_CNT) << 4; + } + config &= ~perf_ibs->cnt_mask; - event->attr.sample_period = max_cnt << 4; - hwc->sample_period = event->attr.sample_period; + event->attr.sample_period = period; + hwc->sample_period = period; } if (!hwc->sample_period) -- 2.39.5