From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B3CF238C2A; Mon, 2 Jun 2025 14:59:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748876348; cv=none; b=tGxQ6z6ZPqYjuFoP/0HZlmjphyBybqxRRIjSLUs8QTXEtJB1nxtF1YGYWH76K8HACgWuUHw6P+dSXaUjMEmzGa56mzaqTvUDyPMUHn1vCBCUKaMtnWjG+xlOeccHwmufOrEDhFeXpnpdZftLSFSftEONRxk6YvcJC/yyuLnLqi0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748876348; c=relaxed/simple; bh=AJGLAyta5h4jt4GzvEGl9VvXrbXTxpUSvESSabxmsik=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MT0EXLINEHncsIzm0r9MEH6BnGBuWgp9Y2weVENVlkWUapVRYMr2Bnu5oDK+WJJSsiYSVd5U3nnhmJkIkOODgY8ZizG8370i6ouJCH9/5P5w6MqzxW4G9hyIjsmLRkJATYV7oPtpROvMqHV8LgSY38vV5vt+++DoZSH4EZw7xbU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=o44u2Y5l; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="o44u2Y5l" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4EF9EC4CEEB; Mon, 2 Jun 2025 14:59:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1748876347; bh=AJGLAyta5h4jt4GzvEGl9VvXrbXTxpUSvESSabxmsik=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o44u2Y5lrAhRs1P13urribCljmr+kFcVK/yKbe4u1S7qYMSa5QIrheuKu0M//vA1m l1WfDZTdL+Krgc2mYpiNvcWN8oq4YqR5t0c+YJExvvr97Epe7UQRpgVrUALjD596mC 4H11MB9lbSTbyXC80Wny6ScXVLspBsffH+HU3maM= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Ravi Bangoria , "Peter Zijlstra (Intel)" , Namhyung Kim , Sasha Levin Subject: [PATCH 5.15 147/207] perf/amd/ibs: Fix perf_ibs_op.cnt_mask for CurCnt Date: Mon, 2 Jun 2025 15:48:39 +0200 Message-ID: <20250602134304.480764081@linuxfoundation.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250602134258.769974467@linuxfoundation.org> References: <20250602134258.769974467@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.15-stable review patch. If anyone has any objections, please let me know. ------------------ From: Ravi Bangoria [ Upstream commit 46dcf85566170d4528b842bf83ffc350d71771fa ] IBS Op uses two counters: MaxCnt and CurCnt. MaxCnt is programmed with the desired sample period. IBS hw generates sample when CurCnt reaches to MaxCnt. The size of these counter used to be 20 bits but later they were extended to 27 bits. The 7 bit extension is indicated by CPUID Fn8000_001B_EAX[6 / OpCntExt]. perf_ibs->cnt_mask variable contains bit masks for MaxCnt and CurCnt. But IBS driver does not set upper 7 bits of CurCnt in cnt_mask even when OpCntExt CPUID bit is set. Fix this. IBS driver uses cnt_mask[CurCnt] bits only while disabling an event. Fortunately, CurCnt bits are not read from MSR while re-enabling the event, instead MaxCnt is programmed with desired period and CurCnt is set to 0. Hence, we did not see any issues so far. Signed-off-by: Ravi Bangoria Signed-off-by: Peter Zijlstra (Intel) Acked-by: Namhyung Kim Link: https://lkml.kernel.org/r/20250115054438.1021-5-ravi.bangoria@amd.com Signed-off-by: Sasha Levin --- arch/x86/events/amd/ibs.c | 3 ++- arch/x86/include/asm/perf_event.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index b605e08f9a8ef..2b83056029942 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -803,7 +803,8 @@ static __init int perf_event_ibs_init(void) if (ibs_caps & IBS_CAPS_OPCNTEXT) { perf_ibs_op.max_period |= IBS_OP_MAX_CNT_EXT_MASK; perf_ibs_op.config_mask |= IBS_OP_MAX_CNT_EXT_MASK; - perf_ibs_op.cnt_mask |= IBS_OP_MAX_CNT_EXT_MASK; + perf_ibs_op.cnt_mask |= (IBS_OP_MAX_CNT_EXT_MASK | + IBS_OP_CUR_CNT_EXT_MASK); } ret = perf_ibs_pmu_init(&perf_ibs_op, "ibs_op"); diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 0e4efcde07831..cbfca9d2c419b 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -417,6 +417,7 @@ struct pebs_xmm { */ #define IBS_OP_CUR_CNT (0xFFF80ULL<<32) #define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32) +#define IBS_OP_CUR_CNT_EXT_MASK (0x7FULL<<52) #define IBS_OP_CNT_CTL (1ULL<<19) #define IBS_OP_VAL (1ULL<<18) #define IBS_OP_ENABLE (1ULL<<17) -- 2.39.5