From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6C392248BE; Mon, 2 Jun 2025 14:48:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748875723; cv=none; b=VcT5e9F1IkgbTi/iufO9rVxgkjKcLm63OEnw+zKpTBrSCJn8u9vgNv2kRIyh00soKQsEZYh2CVr+kamjlpiSftKalwBAHFkokMsDaKu1rxtxH1BtCy6PONPXDECk1iBC93/XUZeDJMpGEbr0/7GZrZFV7WdkHSUojQY02905ugQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748875723; c=relaxed/simple; bh=gl0r2aOHk7vmJVVMYpraoxM6bKkuNZ1xI7hQvlbBrDM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MbGQpFtVU515WvQunZnKZROcpIqIvVS8D8eb76s1Pzg8t70C5Xn7ceMArsT6RckcdMTD+OO2d5a5vyjSBOQf5ni3MfqMl983R+0b9ZXDIQZ073SKuTVVD+AsI0Vx0afQvUN3X7THEy1aC+DPAoUsqnDTA2PVdbH1Wi1IzjR3IW0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=vacRtxAB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="vacRtxAB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E9118C4CEEB; Mon, 2 Jun 2025 14:48:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1748875722; bh=gl0r2aOHk7vmJVVMYpraoxM6bKkuNZ1xI7hQvlbBrDM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vacRtxABeP8URe41ZFBFVhsh23ZsprdqCFjgXHHC5VBSS0Z5oObxXFd5mr8yTnquy 2lBeXDqZFrgb4D0Pd+UyzLCsndfJDcuwhkTXW0hUS3Fj5ZBX+vyyXaf4iXvkts8qAL Z1G8Av5QxUgXq3sLwmepWO9OcP+XY2plCCu8rOD8= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Ravi Bangoria , "Peter Zijlstra (Intel)" , Namhyung Kim , Sasha Levin Subject: [PATCH 5.10 222/270] perf/amd/ibs: Fix perf_ibs_op.cnt_mask for CurCnt Date: Mon, 2 Jun 2025 15:48:27 +0200 Message-ID: <20250602134316.253785488@linuxfoundation.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250602134307.195171844@linuxfoundation.org> References: <20250602134307.195171844@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.10-stable review patch. If anyone has any objections, please let me know. ------------------ From: Ravi Bangoria [ Upstream commit 46dcf85566170d4528b842bf83ffc350d71771fa ] IBS Op uses two counters: MaxCnt and CurCnt. MaxCnt is programmed with the desired sample period. IBS hw generates sample when CurCnt reaches to MaxCnt. The size of these counter used to be 20 bits but later they were extended to 27 bits. The 7 bit extension is indicated by CPUID Fn8000_001B_EAX[6 / OpCntExt]. perf_ibs->cnt_mask variable contains bit masks for MaxCnt and CurCnt. But IBS driver does not set upper 7 bits of CurCnt in cnt_mask even when OpCntExt CPUID bit is set. Fix this. IBS driver uses cnt_mask[CurCnt] bits only while disabling an event. Fortunately, CurCnt bits are not read from MSR while re-enabling the event, instead MaxCnt is programmed with desired period and CurCnt is set to 0. Hence, we did not see any issues so far. Signed-off-by: Ravi Bangoria Signed-off-by: Peter Zijlstra (Intel) Acked-by: Namhyung Kim Link: https://lkml.kernel.org/r/20250115054438.1021-5-ravi.bangoria@amd.com Signed-off-by: Sasha Levin --- arch/x86/events/amd/ibs.c | 3 ++- arch/x86/include/asm/perf_event.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 354d52e17ef55..8525b7960787c 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -808,7 +808,8 @@ static __init int perf_event_ibs_init(void) if (ibs_caps & IBS_CAPS_OPCNTEXT) { perf_ibs_op.max_period |= IBS_OP_MAX_CNT_EXT_MASK; perf_ibs_op.config_mask |= IBS_OP_MAX_CNT_EXT_MASK; - perf_ibs_op.cnt_mask |= IBS_OP_MAX_CNT_EXT_MASK; + perf_ibs_op.cnt_mask |= (IBS_OP_MAX_CNT_EXT_MASK | + IBS_OP_CUR_CNT_EXT_MASK); } ret = perf_ibs_pmu_init(&perf_ibs_op, "ibs_op"); diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index a4e4bbb7795d3..63fc0f50cd38c 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -402,6 +402,7 @@ struct pebs_xmm { */ #define IBS_OP_CUR_CNT (0xFFF80ULL<<32) #define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32) +#define IBS_OP_CUR_CNT_EXT_MASK (0x7FULL<<52) #define IBS_OP_CNT_CTL (1ULL<<19) #define IBS_OP_VAL (1ULL<<18) #define IBS_OP_ENABLE (1ULL<<17) -- 2.39.5