From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16C1129D05; Mon, 2 Jun 2025 14:14:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748873693; cv=none; b=ppBpsmoErLruo7h7cct9JbX19JrkzkfpNXaTV/ZQ7aIHPab/jvQkTrW3BTltZyuFPdRozhAWBZI5QKPu2QFPpTK3YinFlHXv7cweoE5UPl0iJNRH4nfRzEU05m4Z9AGzfjYHKhMYjvi3+1LL4krRSpWvsogSbcejIAXmzwF0R0k= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748873693; c=relaxed/simple; bh=x4Vuq/7te+wuWO4OQr92QwsJlHFJpiGG83OVWTYcBoQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IBXu5w9Dw6yVzlgTfqLmcd5XnrF/agZrTzu2w2jgtWcvNO3xXeaXVDM3GicQ01DP6f8u/GGsPjaUUj2Ucgzf3T33Oy7wH7epRzEd6lVzL42XScPdwMZIKql/cF//JAVnGIwdUXW/krHFlKvhpLDT8LqxIc33X+/pt4x1gXufaps= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=JD+Vnt+k; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="JD+Vnt+k" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9A4EBC4CEEB; Mon, 2 Jun 2025 14:14:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1748873693; bh=x4Vuq/7te+wuWO4OQr92QwsJlHFJpiGG83OVWTYcBoQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JD+Vnt+kVX+c4Iy3zU97CzlYcMDjhuEo3sSa4qe7YsblKZhq5uL6/FdBzsOkEWUYx rQH/75mfE9oHLMOOVHFvQnEzNTDa71gDs6+H33XyDfPc9mxc7c0L2gStMSpfhrDslF CAPogDIag0yOBe4zOjlhdpOVansjWgEIj+8gVBBU= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Shahar Shitrit , Tariq Toukan , Mateusz Polchlopek , Jakub Kicinski , Sasha Levin Subject: [PATCH 6.6 221/444] net/mlx5: Modify LSB bitmask in temperature event to include only the first bit Date: Mon, 2 Jun 2025 15:44:45 +0200 Message-ID: <20250602134349.877138478@linuxfoundation.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250602134340.906731340@linuxfoundation.org> References: <20250602134340.906731340@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Shahar Shitrit [ Upstream commit 633f16d7e07c129a36b882c05379e01ce5bdb542 ] In the sensor_count field of the MTEWE register, bits 1-62 are supported only for unmanaged switches, not for NICs, and bit 63 is reserved for internal use. To prevent confusing output that may include set bits that are not relevant to NIC sensors, we update the bitmask to retain only the first bit, which corresponds to the sensor ASIC. Signed-off-by: Shahar Shitrit Signed-off-by: Tariq Toukan Reviewed-by: Mateusz Polchlopek Link: https://patch.msgid.link/20250213094641.226501-4-tariqt@nvidia.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/mellanox/mlx5/core/events.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/events.c b/drivers/net/ethernet/mellanox/mlx5/core/events.c index 3ec892d51f57d..0f4763dab5d25 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/events.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/events.c @@ -163,6 +163,10 @@ static int temp_warn(struct notifier_block *nb, unsigned long type, void *data) u64 value_msb; value_lsb = be64_to_cpu(eqe->data.temp_warning.sensor_warning_lsb); + /* bit 1-63 are not supported for NICs, + * hence read only bit 0 (asic) from lsb. + */ + value_lsb &= 0x1; value_msb = be64_to_cpu(eqe->data.temp_warning.sensor_warning_msb); mlx5_core_warn(events->dev, -- 2.39.5