From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 504171E0DD8; Mon, 2 Jun 2025 14:21:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748874067; cv=none; b=QIzGa4RuIaZF19NzFIk7sDjQM2GGhYQznRfpD7ZDuxlAZF65+353uSyyo1var0hvPmAQvVSSu9BZVeDXcBFKnVrLjtuWKJe0047Gf2EO4tnZBKuUU8AUHKJQsHTWFtZWfIhDl6SySJiScpiifGypNBRCDrtc998AuFk9L0ItLkI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748874067; c=relaxed/simple; bh=XOxsM/af8fEGG+BELj1zLsbrZFiENL74phBn/42PMCg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FJDZnyypbyb86QvJdDgcjdS05OxgummMGY3ajHOcrGrMPKH8RLC6LXNQPjhCTTltSNMwarwjE7B4AjGe0wjpjJ+1lMQsuOs7OkDUBhatCG6F5rIsDZz7tBeGj4rGfN35149a2h7n65JYrtugembPUV/hCizxe2ksIGdgzlCNk4g= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=0oCk+z7I; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="0oCk+z7I" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D779DC4CEEB; Mon, 2 Jun 2025 14:21:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1748874067; bh=XOxsM/af8fEGG+BELj1zLsbrZFiENL74phBn/42PMCg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=0oCk+z7IYX6TD7FeSCPJysmhOrB2JdrXACIxrvTK+T/3MLLorCnznEl2pBv6NqkQA DiC5OF1bhrUNIPGBoh2vp7GxlNbf9Ot2U+icvb043QwVXhXrOdZBImyES01pKAkgGP 1PfU2J5uBplMGpeCMyZMsfWaheVo3Jum8grASLQ4= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Paul Kocialkowski , Andrew Lunn , Corentin LABBE , Jakub Kicinski , Sasha Levin Subject: [PATCH 6.6 347/444] net: dwmac-sun8i: Use parsed internal PHY address instead of 1 Date: Mon, 2 Jun 2025 15:46:51 +0200 Message-ID: <20250602134355.021705817@linuxfoundation.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250602134340.906731340@linuxfoundation.org> References: <20250602134340.906731340@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Paul Kocialkowski [ Upstream commit 47653e4243f2b0a26372e481ca098936b51ec3a8 ] While the MDIO address of the internal PHY on Allwinner sun8i chips is generally 1, of_mdio_parse_addr is used to cleanly parse the address from the device-tree instead of hardcoding it. A commit reworking the code ditched the parsed value and hardcoded the value 1 instead, which didn't really break anything but is more fragile and not future-proof. Restore the initial behavior using the parsed address returned from the helper. Fixes: 634db83b8265 ("net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs") Signed-off-by: Paul Kocialkowski Reviewed-by: Andrew Lunn Acked-by: Corentin LABBE Tested-by: Corentin LABBE Link: https://patch.msgid.link/20250519164936.4172658-1-paulk@sys-base.io Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index 63998d65fef8e..9377b05bfc71e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -966,7 +966,7 @@ static int sun8i_dwmac_set_syscon(struct device *dev, /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY * address. No need to mask it again. */ - reg |= 1 << H3_EPHY_ADDR_SHIFT; + reg |= ret << H3_EPHY_ADDR_SHIFT; } else { /* For SoCs without internal PHY the PHY selection bit should be * set to 0 (external PHY). -- 2.39.5