From: Matthew Auld <matthew.auld@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
stable@vger.kernel.org
Subject: [PATCH 2/2] drm/xe: move DPT l2 flush to a more sensible place
Date: Fri, 6 Jun 2025 11:45:48 +0100 [thread overview]
Message-ID: <20250606104546.1996818-4-matthew.auld@intel.com> (raw)
In-Reply-To: <20250606104546.1996818-3-matthew.auld@intel.com>
Only need the flush for DPT host updates here. Normal GGTT updates don't
need special flush.
Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: <stable@vger.kernel.org> # v6.12+
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index 461ecdfdb742..b16a6e3ff4b4 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -165,6 +165,9 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
vma->dpt = dpt;
vma->node = dpt->ggtt_node[tile0->id];
+
+ /* Ensure DPT writes are flushed */
+ xe_device_l2_flush(xe);
return 0;
}
@@ -334,8 +337,6 @@ static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb,
if (ret)
goto err_unpin;
- /* Ensure DPT writes are flushed */
- xe_device_l2_flush(xe);
return vma;
err_unpin:
--
2.49.0
next prev parent reply other threads:[~2025-06-06 10:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-06 10:45 [PATCH 1/2] drm/xe: Move DSB l2 flush to a more sensible place Matthew Auld
2025-06-06 10:45 ` Matthew Auld [this message]
2025-06-17 16:35 ` [PATCH 2/2] drm/xe: move DPT " Ville Syrjälä
2025-06-18 18:59 ` Lucas De Marchi
2025-06-06 15:19 ` [PATCH 1/2] drm/xe: Move DSB " Matthew Auld
2025-06-17 16:26 ` Ville Syrjälä
2025-06-18 19:06 ` Lucas De Marchi
2025-06-24 17:47 ` Lucas De Marchi
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