Re: [PATCH 5.10 v2 02/16] x86/bhi: Define SPEC_CTRL_BHI_DIS_S

[Sasha Levin <sashal@kernel.org>]

[ Sasha's backport helper bot ]

Hi,

✅ All tests passed successfully. No issues detected.
No action required from the submitter.

The upstream commit SHA1 provided is correct: 0f4a837615ff925ba62648d280a861adf1582df7

WARNING: Author mismatch between patch and upstream commit:
Backport author: Pawan Gupta<pawan.kumar.gupta@linux.intel.com>
Commit author: Daniel Sneddon<daniel.sneddon@linux.intel.com>

Status in newer kernel trees:
6.15.y | Present (exact SHA1)
6.12.y | Present (exact SHA1)
6.6.y | Present (different SHA1: c6e3d590d051)
6.1.y | Present (different SHA1: 29c50bb6fbe4)
5.15.y | Present (different SHA1: a9ca0e34a406)

Note: The patch differs from the upstream commit:
---
1:  0f4a837615ff9 ! 1:  3542cbefb1a99 x86/bhi: Define SPEC_CTRL_BHI_DIS_S
    @@ Metadata
      ## Commit message ##
         x86/bhi: Define SPEC_CTRL_BHI_DIS_S
     
    +    commit 0f4a837615ff925ba62648d280a861adf1582df7 upstream.
    +
         Newer processors supports a hardware control BHI_DIS_S to mitigate
         Branch History Injection (BHI). Setting BHI_DIS_S protects the kernel
         from userspace BHI attacks without having to manually overwrite the
    @@ Commit message
         Define MSR_SPEC_CTRL bit BHI_DIS_S and its enumeration CPUID.BHI_CTRL.
         Mitigation is enabled later.
     
    -    Signed-off-by: Daniel Sneddon <daniel.sneddon@linux.intel.com>
    -    Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
    -    Signed-off-by: Daniel Sneddon <daniel.sneddon@linux.intel.com>
         Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
         Reviewed-by: Alexandre Chartre <alexandre.chartre@oracle.com>
         Reviewed-by: Josh Poimboeuf <jpoimboe@kernel.org>
    +    Signed-off-by: Daniel Sneddon <daniel.sneddon@linux.intel.com>
    +    Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
     
      ## arch/x86/include/asm/cpufeatures.h ##
     @@
    -  */
    - #define X86_FEATURE_AMD_LBR_PMC_FREEZE	(21*32+ 0) /* AMD LBR and PMC Freeze */
    - #define X86_FEATURE_CLEAR_BHB_LOOP	(21*32+ 1) /* "" Clear branch history at syscall entry using SW loop */
    -+#define X86_FEATURE_BHI_CTRL		(21*32+ 2) /* "" BHI_DIS_S HW control available */
    - 
    - /*
    -  * BUG word(s)
    + #define X86_FEATURE_FENCE_SWAPGS_KERNEL	(11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
    + #define X86_FEATURE_SPLIT_LOCK_DETECT	(11*32+ 6) /* #AC for split lock */
    + #define X86_FEATURE_PER_THREAD_MBA	(11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
    +-/* FREE!				(11*32+ 8) */
    ++#define X86_FEATURE_BHI_CTRL		(11*32+ 8) /* "" BHI_DIS_S HW control available */
    + /* FREE!				(11*32+ 9) */
    + #define X86_FEATURE_ENTRY_IBPB		(11*32+10) /* "" Issue an IBPB on kernel entry */
    + #define X86_FEATURE_RRSBA_CTRL		(11*32+11) /* "" RET prediction control */
     
      ## arch/x86/include/asm/msr-index.h ##
     @@
    @@ arch/x86/include/asm/msr-index.h
     
      ## arch/x86/kernel/cpu/scattered.c ##
     @@ arch/x86/kernel/cpu/scattered.c: static const struct cpuid_bit cpuid_bits[] = {
    + 	{ X86_FEATURE_APERFMPERF,       CPUID_ECX,  0, 0x00000006, 0 },
      	{ X86_FEATURE_EPB,		CPUID_ECX,  3, 0x00000006, 0 },
    - 	{ X86_FEATURE_INTEL_PPIN,	CPUID_EBX,  0, 0x00000007, 1 },
      	{ X86_FEATURE_RRSBA_CTRL,	CPUID_EDX,  2, 0x00000007, 2 },
     +	{ X86_FEATURE_BHI_CTRL,		CPUID_EDX,  4, 0x00000007, 2 },
      	{ X86_FEATURE_CQM_LLC,		CPUID_EDX,  1, 0x0000000f, 0 },
      	{ X86_FEATURE_CQM_OCCUP_LLC,	CPUID_EDX,  0, 0x0000000f, 1 },
      	{ X86_FEATURE_CQM_MBM_TOTAL,	CPUID_EDX,  1, 0x0000000f, 1 },
    -
    - ## arch/x86/kvm/reverse_cpuid.h ##
    -@@ arch/x86/kvm/reverse_cpuid.h: enum kvm_only_cpuid_leafs {
    - #define X86_FEATURE_IPRED_CTRL		KVM_X86_FEATURE(CPUID_7_2_EDX, 1)
    - #define KVM_X86_FEATURE_RRSBA_CTRL	KVM_X86_FEATURE(CPUID_7_2_EDX, 2)
    - #define X86_FEATURE_DDPD_U		KVM_X86_FEATURE(CPUID_7_2_EDX, 3)
    --#define X86_FEATURE_BHI_CTRL		KVM_X86_FEATURE(CPUID_7_2_EDX, 4)
    -+#define KVM_X86_FEATURE_BHI_CTRL	KVM_X86_FEATURE(CPUID_7_2_EDX, 4)
    - #define X86_FEATURE_MCDT_NO		KVM_X86_FEATURE(CPUID_7_2_EDX, 5)
    - 
    - /* CPUID level 0x80000007 (EDX). */
    -@@ arch/x86/kvm/reverse_cpuid.h: static __always_inline u32 __feature_translate(int x86_feature)
    - 	KVM_X86_TRANSLATE_FEATURE(CONSTANT_TSC);
    - 	KVM_X86_TRANSLATE_FEATURE(PERFMON_V2);
    - 	KVM_X86_TRANSLATE_FEATURE(RRSBA_CTRL);
    -+	KVM_X86_TRANSLATE_FEATURE(BHI_CTRL);
    - 	default:
    - 		return x86_feature;
    - 	}
---

Results of testing on various branches:

| Branch                    | Patch Apply | Build Test |
|---------------------------|-------------|------------|
| stable/linux-5.15.y       |  Success    |  Success   |