From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9789B38DE1; Mon, 23 Jun 2025 21:18:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750713516; cv=none; b=n3viGzN77ODWSgVwky0xrR8FLvU5K4DDOGHGvCnoBlFSqfz5omW8+fioYTvOnmp+leI/IuioD4nxjAl1JhwHjISr7mG4qgP8l+5BNs6PhrUkmiWYgZtvYq6yYalb+N7tX+xDYGUypOgT/R62/ea7YqWgoCL7c4183x6bzBhEy8M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750713516; c=relaxed/simple; bh=ZVpBjR/kpeL/5/zvVmu9EDOr6aCAQEJE3HzpyFFXi2M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JScW2zjn3cSFxPxIaCvSAxi7oMqMn2IiGFLj9r4JZUFPU9JonAg5pMGbdTeU+MVlOyrvatpQkKfpiydN4erByz0AfT6rVnLRz7qjUnf3MLTH7vQtd+6JQl3iJf13ZomaJ56ahY1bBdetv6qAcQTiQ7R8SQauDP4aTg7/Fa374aM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=VvVy7OLv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="VvVy7OLv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3016CC4CEEA; Mon, 23 Jun 2025 21:18:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1750713516; bh=ZVpBjR/kpeL/5/zvVmu9EDOr6aCAQEJE3HzpyFFXi2M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VvVy7OLvuWofEtTRVE0LAevGOfTQcn9RI5OrM4OlEDQ6P+npYSScjtflfw08zM2Rp 4G6dn9yCSyZD0ICfdxdI6urV86+C3YRFBn9gOj/UwUSQ2fhiXRUuQeLADZaOvm5jtT HdHJV6sCddyt8PJWLqS4MLI3ILcfNtcB3vdTcNK0= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Robert Nelson , Shengyu Qu , Tony Lindgren , "Nobuhiro Iwamatsu (CIP)" Subject: [PATCH 5.4 210/222] ARM: dts: am335x-bone-common: Add GPIO PHY reset on revision C3 board Date: Mon, 23 Jun 2025 15:09:05 +0200 Message-ID: <20250623130618.617190550@linuxfoundation.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250623130611.896514667@linuxfoundation.org> References: <20250623130611.896514667@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.4-stable review patch. If anyone has any objections, please let me know. ------------------ From: Shengyu Qu commit 623cef652768860bd5f205fb7b741be278585fba upstream. This patch adds ethernet PHY reset GPIO config for Beaglebone Black series boards with revision C3. This fixes a random phy startup failure bug discussed at [1]. The GPIO pin used for reset is not used on older revisions, so it is ok to apply to all board revisions. The reset timing was discussed and tested at [2]. [1] https://forum.digikey.com/t/ethernet-device-is-not-detecting-on-ubuntu-20-04-lts-on-bbg/19948 [2] https://forum.beagleboard.org/t/recognizing-a-beaglebone-black-rev-c3-board/31249/ Signed-off-by: Robert Nelson Signed-off-by: Shengyu Qu Message-ID: Signed-off-by: Tony Lindgren Signed-off-by: Nobuhiro Iwamatsu (CIP) Signed-off-by: Greg Kroah-Hartman --- arch/arm/boot/dts/am335x-bone-common.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -145,6 +145,8 @@ /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + /* Added to support GPIO controlled PHY reset */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE7) >; }; @@ -153,6 +155,8 @@ /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) + /* Added to support GPIO controlled PHY reset */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; @@ -396,6 +400,10 @@ ethphy0: ethernet-phy@0 { reg = <0>; + /* Support GPIO reset on revision C3 boards */ + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <300>; + reset-deassert-us = <6500>; }; };