From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E6452AEE4; Mon, 23 Jun 2025 21:43:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750715014; cv=none; b=PqTC79dd4c9WjZfOMJAe/nlwlPsjF/8oA0YoSjG1HrNi6tBl4EPhGw3LpVlQnZ6dodOIIILSyMfLWG6THIQ9PBarDXHX8oKhwcXMihto4UQvUwlrNtQUQp7s08O1yNMp203DJid3NRQjkSouWoaXmD/O/Ae3upv2FeTR0KL+0ew= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750715014; c=relaxed/simple; bh=0MfK6WPFvizMaT3Q8mRIM82cdzkw7bKTOXlMuz69Fas=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hLF+KjqKFDzXG16J1poYod60keF4UJJjr5/VtX37PfemVSufza6GrGBZHi9H82j0gUmaiTgwz/KJZ6lvTOQaYt3Iq/J1ZM+bJdE5loKY5pIiFpFx8ip4AVP3D3AJ+Y5l2/uUFI5SoZWsc5XnGImBz4VilLRYRhuAfZYuDTyKEZU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=kMc3qFZK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="kMc3qFZK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EC9BCC4CEEA; Mon, 23 Jun 2025 21:43:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1750715014; bh=0MfK6WPFvizMaT3Q8mRIM82cdzkw7bKTOXlMuz69Fas=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kMc3qFZKZDI0/xlRt21aQl1bwOfkhyBrU/co1okXqUyz1vDgf2ck+dQBxgZqPVRw9 76qhYluLGijWpQLc7Bauqz8LM2SRaQ6K2LGUBFwDORkMb2GtR5txcpKgjXMaoCrSR6 yA55qGVHIQKRMAKGPZXGmWHdOyy4gV86giLQdHWk= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Niklas Cassel , Manivannan Sadhasivam , Bjorn Helgaas , Wilfred Mallawa , Damien Le Moal Subject: [PATCH 6.12 150/414] PCI: cadence-ep: Correct PBA offset in .set_msix() callback Date: Mon, 23 Jun 2025 15:04:47 +0200 Message-ID: <20250623130645.797099665@linuxfoundation.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250623130642.015559452@linuxfoundation.org> References: <20250623130642.015559452@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Niklas Cassel commit c8bcb01352a86bc5592403904109c22b66bd916e upstream. While cdns_pcie_ep_set_msix() writes the Table Size field correctly (N-1), the calculation of the PBA offset is wrong because it calculates space for (N-1) entries instead of N. This results in the following QEMU error when using PCI passthrough on a device which relies on the PCI endpoint subsystem: failed to add PCI capability 0x11[0x50]@0xb0: table & pba overlap, or they don't fit in BARs, or don't align Fix the calculation of PBA offset in the MSI-X capability. [bhelgaas: more specific subject and commit log] Fixes: 3ef5d16f50f8 ("PCI: cadence: Add MSI-X support to Endpoint driver") Signed-off-by: Niklas Cassel Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Helgaas Reviewed-by: Wilfred Mallawa Reviewed-by: Damien Le Moal Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20250514074313.283156-10-cassel@kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/pci/controller/cadence/pcie-cadence-ep.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -292,13 +292,14 @@ static int cdns_pcie_ep_set_msix(struct struct cdns_pcie *pcie = &ep->pcie; u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 val, reg; + u16 actual_interrupts = interrupts + 1; fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); reg = cap + PCI_MSIX_FLAGS; val = cdns_pcie_ep_fn_readw(pcie, fn, reg); val &= ~PCI_MSIX_FLAGS_QSIZE; - val |= interrupts; + val |= interrupts; /* 0's based value */ cdns_pcie_ep_fn_writew(pcie, fn, reg, val); /* Set MSIX BAR and offset */ @@ -308,7 +309,7 @@ static int cdns_pcie_ep_set_msix(struct /* Set PBA BAR and offset. BAR must match MSIX BAR */ reg = cap + PCI_MSIX_PBA; - val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir; + val = (offset + (actual_interrupts * PCI_MSIX_ENTRY_SIZE)) | bir; cdns_pcie_ep_fn_writel(pcie, fn, reg, val); return 0;