From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFF092E3AE5; Tue, 15 Jul 2025 13:57:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752587867; cv=none; b=fdqYGXtfq23+ybTUO5POjR7gZET55JKSsf1iYrRq1PmNVxTvT92DCB5L6Dro6P1kYrHKx5qtXipjYhS4CzsJILNEKgZWhWwqbEFkbSdwEqjgo115tMXsTuG1Ozjv4vq64bPBnJHwC3Gtfrg9XuN0pumCYviEbQq4hLaDznxnmLc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752587867; c=relaxed/simple; bh=ZEL2p+V45oa3hfe8RMoWvZzyKCWbvyGYF4seJGFa6So=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AWYOMI6TmUgtFXT+Xk2bTgipIyUlr8QOvi0u3HS1hqXaOTrf4OBTw/C52Ok127EYZEJWmomnCvf9q3oWDFvtas9bHO91n7yCC+Qo9Dbdz3VtOyjzp/wdGci2aP18KBgGvCGcTww5zN0aqZW4KR6FcQV8C8oJQAVjqtfkw9eUlig= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=2tGZEtqn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="2tGZEtqn" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6378CC4CEE3; Tue, 15 Jul 2025 13:57:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1752587867; bh=ZEL2p+V45oa3hfe8RMoWvZzyKCWbvyGYF4seJGFa6So=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=2tGZEtqnu419BUAD2pJUJsfelvATBLbe6tuE3XDnqkA5F5HDwaE1dzmui3kzopWiy G5PEk5CQOUlWGlhl9j8woRw7dam2GGRecMc+uyog5PHFSdVc+hW1hsoFCjp7QNAN3z ivmrzQqgXBNtEFrBRJ6jTTMt/zxndHpcsg+tWVyU= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Bjorn Andersson , Bartosz Golaszewski , Linus Walleij Subject: [PATCH 5.10 174/208] pinctrl: qcom: msm: mark certain pins as invalid for interrupts Date: Tue, 15 Jul 2025 15:14:43 +0200 Message-ID: <20250715130817.942259982@linuxfoundation.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250715130810.830580412@linuxfoundation.org> References: <20250715130810.830580412@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.10-stable review patch. If anyone has any objections, please let me know. ------------------ From: Bartosz Golaszewski commit 93712205ce2f1fb047739494c0399a26ea4f0890 upstream. On some platforms, the UFS-reset pin has no interrupt logic in TLMM but is nevertheless registered as a GPIO in the kernel. This enables the user-space to trigger a BUG() in the pinctrl-msm driver by running, for example: `gpiomon -c 0 113` on RB2. The exact culprit is requesting pins whose intr_detection_width setting is not 1 or 2 for interrupts. This hits a BUG() in msm_gpio_irq_set_type(). Potentially crashing the kernel due to an invalid request from user-space is not optimal, so let's go through the pins and mark those that would fail the check as invalid for the irq chip as we should not even register them as available irqs. This function can be extended if we determine that there are more corner-cases like this. Fixes: f365be092572 ("pinctrl: Add Qualcomm TLMM driver") Cc: stable@vger.kernel.org Reviewed-by: Bjorn Andersson Signed-off-by: Bartosz Golaszewski Link: https://lore.kernel.org/20250612091448.41546-1-brgl@bgdev.pl Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman --- drivers/pinctrl/qcom/pinctrl-msm.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -949,6 +949,25 @@ static bool msm_gpio_needs_dual_edge_par test_bit(d->hwirq, pctrl->skip_wake_irqs); } +static void msm_gpio_irq_init_valid_mask(struct gpio_chip *gc, + unsigned long *valid_mask, + unsigned int ngpios) +{ + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_pingroup *g; + int i; + + bitmap_fill(valid_mask, ngpios); + + for (i = 0; i < ngpios; i++) { + g = &pctrl->soc->groups[i]; + + if (g->intr_detection_width != 1 && + g->intr_detection_width != 2) + clear_bit(i, valid_mask); + } +} + static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); @@ -1307,6 +1326,7 @@ static int msm_gpio_init(struct msm_pinc girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_bad_irq; girq->parents[0] = pctrl->irq; + girq->init_valid_mask = msm_gpio_irq_init_valid_mask; ret = gpiochip_add_data(&pctrl->chip, pctrl); if (ret) {