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[83.28.45.133]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af635ad7d95sm567005366b.122.2025.07.29.03.18.02 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Tue, 29 Jul 2025 03:18:03 -0700 (PDT) Date: Tue, 29 Jul 2025 12:17:59 +0200 From: =?UTF-8?B?TWljaGHFgg==?= Pecio To: Marek Vasut Cc: linux-usb@vger.kernel.org, Geert Uytterhoeven , Greg Kroah-Hartman , Mathias Nyman , Vinod Koul , stable@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH] usb: renesas-xhci: Fix External ROM access timeouts Message-ID: <20250729121759.0e9df735@foxbook> In-Reply-To: <20250727154516.11599-1-marek.vasut+renesas@mailbox.org> References: <20250727154516.11599-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Hi, On Sun, 27 Jul 2025 17:44:16 +0200, Marek Vasut wrote: > Increase the External ROM access timeouts to prevent failures during > programming of External SPI EEPROM chips. The current timeouts are > too short for some SPI EEPROMs used with uPD720201 controllers. > > The current timeout for Chip Erase in renesas_rom_erase() is 100 ms , > the current timeout for Sector Erase issued by the controller before > Page Program in renesas_fw_download_image() is also 100 ms. Neither > timeout is sufficient for e.g. the Macronix MX25L5121E or MX25V5126F. Out of curiosity, who uses this ROM update functionality and why? It seems weird to write nonvolatile memories in a PCI probe routine. Boards or PCIe cards fitted with ROMs are programmed with working firmware at the factory and there ought to be no need to touch that. And if you want to update this FW, dropping a file in /lib/firmware/ and loading a kernel module is not the usual (or convenient) UI... Regards, Michal