From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE9293126CA for ; Fri, 22 Aug 2025 17:00:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755882023; cv=none; b=qmB6C0SyAR3s5RfnzTukm3QnuZw/iCgrbXXwy88gDfKHcsAVBIV46GySbiaeHEP13VLVOrFaFFbV7dWx1XhzotNz3/cPckW+oW/VLDCXE9EpJBOU7t1NuoJa1MBWNtyup7pReb9cenGKD4z0vrGAKKa2mQZn7bgu1YOgsxsF2rc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755882023; c=relaxed/simple; bh=BDmCzcPREXNcsqW31e5vBNp7OgRyEc+cQqJboD/gR40=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rLAYz9w+uB5vCpCzQmp6MjwJg4EV1UQyw2+Wx+vsYHWBQJeUdIWm6dT3ho5QGYRtGSW2ufHRy7laoafLPDFMBlyX2DD8s3DUcBd7GHo2Xzmf/RQlPEYVtC5vtHNUsAwEY2zsddkj0cob01WAjst3RARO59ZQC8WeT/uu+QXVJd4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SQgE5Oh7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SQgE5Oh7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 39168C4CEED; Fri, 22 Aug 2025 17:00:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755882022; bh=BDmCzcPREXNcsqW31e5vBNp7OgRyEc+cQqJboD/gR40=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SQgE5Oh7O+nTE1c1fK/sjwfl4bcbGk5kkDknePBCckCyQo9u6CiO6WaEGgTKzDb4P yutT2GUHouCm8+a6tpGxPWo5GggBcwNnFkK5JK8LFDwq9ShyTwpUZEr1ghF6axzMUu JmM7QV5gzVkBYy4TYqvsPS92CW0QLb3EnooFa5Z1FWmatstP2pADTSI480X1A06PCZ UzkMfb98L1xuJKlINcC06dGk+ERQDyYD8MXHFmBMmoqOiLyHgJSkTh+8PE7k/k7Qbz QZsPuBAAUcoGfvAQNxDIDcFAWuCbKIw8o9Nlpg/pF+U8YwrOAU4ZH2Vs2apbCg7qxK 9zSkSqZZC6f+A== From: Sasha Levin To: stable@vger.kernel.org Cc: Archana Patni , Bart Van Assche , "Martin K. Petersen" , Sasha Levin Subject: [PATCH 5.15.y] scsi: ufs: ufs-pci: Fix hibernate state transition for Intel MTL-like host controllers Date: Fri, 22 Aug 2025 13:00:19 -0400 Message-ID: <20250822170019.1318372-1-sashal@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: <2025082151-ethics-sponsor-e016@gregkh> References: <2025082151-ethics-sponsor-e016@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Archana Patni [ Upstream commit 4428ddea832cfdb63e476eb2e5c8feb5d36057fe ] UFSHCD core disables the UIC completion interrupt when issuing UIC hibernation commands, and re-enables it afterwards if it was enabled to start with, refer ufshcd_uic_pwr_ctrl(). For Intel MTL-like host controllers, accessing the register to re-enable the interrupt disrupts the state transition. Use hibern8_notify variant operation to disable the interrupt during the entire hibernation, thereby preventing the disruption. Fixes: 4049f7acef3e ("scsi: ufs: ufs-pci: Add support for Intel MTL") Cc: stable@vger.kernel.org Signed-off-by: Archana Patni Link: https://lore.kernel.org/r/20250723165856.145750-2-adrian.hunter@intel.com Reviewed-by: Bart Van Assche Signed-off-by: Martin K. Petersen [ Adapted file path from drivers/ufs/host/ to drivers/scsi/ufs/ ] Signed-off-by: Sasha Levin --- drivers/scsi/ufs/ufshcd-pci.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/scsi/ufs/ufshcd-pci.c b/drivers/scsi/ufs/ufshcd-pci.c index 0920530a72d2..11071c132c1d 100644 --- a/drivers/scsi/ufs/ufshcd-pci.c +++ b/drivers/scsi/ufs/ufshcd-pci.c @@ -203,6 +203,32 @@ static int ufs_intel_lkf_apply_dev_quirks(struct ufs_hba *hba) return ret; } +static void ufs_intel_ctrl_uic_compl(struct ufs_hba *hba, bool enable) +{ + u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); + + if (enable) + set |= UIC_COMMAND_COMPL; + else + set &= ~UIC_COMMAND_COMPL; + ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); +} + +static void ufs_intel_mtl_h8_notify(struct ufs_hba *hba, + enum uic_cmd_dme cmd, + enum ufs_notify_change_status status) +{ + /* + * Disable UIC COMPL INTR to prevent access to UFSHCI after + * checking HCS.UPMCRS + */ + if (status == PRE_CHANGE && cmd == UIC_CMD_DME_HIBER_ENTER) + ufs_intel_ctrl_uic_compl(hba, false); + + if (status == POST_CHANGE && cmd == UIC_CMD_DME_HIBER_EXIT) + ufs_intel_ctrl_uic_compl(hba, true); +} + #define INTEL_ACTIVELTR 0x804 #define INTEL_IDLELTR 0x808 @@ -476,6 +502,7 @@ static struct ufs_hba_variant_ops ufs_intel_mtl_hba_vops = { .init = ufs_intel_mtl_init, .exit = ufs_intel_common_exit, .hce_enable_notify = ufs_intel_hce_enable_notify, + .hibern8_notify = ufs_intel_mtl_h8_notify, .link_startup_notify = ufs_intel_link_startup_notify, .resume = ufs_intel_resume, .device_reset = ufs_intel_device_reset, -- 2.50.1