From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5002218E025 for ; Fri, 22 Aug 2025 19:05:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755889531; cv=none; b=rsANOVoZMY45boovTyid2tFCjKOzBoiR3/d32P3rwMIOnyFuhKEbkJ43wHN3282jxVuL/4RS+2sqnAzT1/eCwXBSHPRDf7TIY+2hi+bZAJTKjCItLf+w4UumaqhDwAqVqzSknsWoL13GcCbpDjnOeE7yWfVkEmES3t6BER3PPSE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755889531; c=relaxed/simple; bh=LjuYxnJvlWiwYzH9XsxAticWSvE6fdZIwCCrwdtP2pw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AS3xYnXWFPmVIUnPnaIES5bWBXqZoWSrRTNNuQXYnJbtB65Wo/UL8q4vAQxzW/3H6PVApPr1osQW4vepjw9JDXXb9xVApL5QiU0J6Aq910GfWci/rpZS4ooHuS83IXXWi4eXcsr5hcl/ri5jbJeqoE/My4K2DVjFwMwEablNE94= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jFD1Lvs5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jFD1Lvs5" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4EA27C116B1; Fri, 22 Aug 2025 19:05:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755889530; bh=LjuYxnJvlWiwYzH9XsxAticWSvE6fdZIwCCrwdtP2pw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jFD1Lvs59I5ulYyIjOMhfEvAcl0EXiNVWYRvl3nY4bbuw5hdr/Tytur4mgOedLGTs Ogja7TqUidjq3MXY20W+DuCEXEYmJcgQgqi4yFs76fIO8lv2XdUO6axMW8qGlVK+3w 01XZUa1BLTY3k9OpZKk255yklCF3aGAKcIf3WecfMKpSM5YiJLZGcS0wTZcHLd8MNa FjygJfukWTbogbY0WXXyLIaN9gvuplDgjT6z4fgb8s0enAXnNR0YNT2yyr78VimL43 pw6JD6PCx0n5F+na2rmHrfloofRlKrF74WU/Tdu2Ou/BX5jQF13jSX2v/hJmh7jIBX mDPdDb4t8roIg== From: Sasha Levin To: stable@vger.kernel.org Cc: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , AngeloGioacchino Del Regno , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Sasha Levin Subject: [PATCH 5.4.y 3/3] pwm: mediatek: Fix duty and period setting Date: Fri, 22 Aug 2025 15:05:27 -0400 Message-ID: <20250822190527.1408882-3-sashal@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250822190527.1408882-1-sashal@kernel.org> References: <2025082143-creature-relay-7247@gregkh> <20250822190527.1408882-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Uwe Kleine-König [ Upstream commit f21d136caf8171f94159d975ea4620c164431bd9 ] The period generated by the hardware is (PWMDWIDTH + 1) << CLKDIV) / freq according to my tests with a signal analyser and also the documentation. The current algorithm doesn't consider the `+ 1` part and so configures slightly too high periods. The same issue exists for the duty cycle setting. So subtract 1 from both the register values for period and duty cycle. If period is 0, bail out, if duty_cycle is 0, just disable the PWM which results in a constant low output. Fixes: caf065f8fd58 ("pwm: Add MediaTek PWM support") Signed-off-by: Uwe Kleine-König Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/6d1fa87a76f8020bfe3171529b8e19baffceab10.1753717973.git.u.kleine-koenig@baylibre.com Cc: stable@vger.kernel.org Signed-off-by: Uwe Kleine-König Signed-off-by: Sasha Levin --- drivers/pwm/pwm-mediatek.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 203e5c13a0d1..c2235daa5bcd 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -168,7 +168,10 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, do_div(resolution, clk_rate); cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution); - while (cnt_period > 8191) { + if (!cnt_period) + return -EINVAL; + + while (cnt_period > 8192) { resolution *= 2; clkdiv++; cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, @@ -191,9 +194,16 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, } cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution); + pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); - pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period); - pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); + pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period - 1); + + if (cnt_duty) { + pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty - 1); + pwm_mediatek_enable(chip, pwm); + } else { + pwm_mediatek_disable(chip, pwm); + } out: pwm_mediatek_clk_disable(chip, pwm); @@ -222,11 +232,8 @@ static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm, if (err) return err; - if (!pwm->state.enabled) { + if (!pwm->state.enabled) err = pwm_mediatek_clk_enable(chip, pwm); - if (!err) - pwm_mediatek_enable(chip, pwm); - } return err; } -- 2.50.1