From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98E59258ECD for ; Sat, 23 Aug 2025 14:32:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755959568; cv=none; b=cmXXL2hNf5Serwb7BM+JB1OywnZfcAGjZ+3lnBGF8LPDL1yvASwAavjEEY7lq2vyMA4QGb6BwCc0uNF316f7HFXVouP7FPA189NUNvR5HfGrRlycSwTm7XnkM5B13FkAeMUlIwuIE898Lu9U0vpxgPQRGZkC+lH0Qs/QAxCxQYg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755959568; c=relaxed/simple; bh=p4K5CW7Fi9zPO5eeTdpL/9ZRiA50DYrX9Hr7mJ8NXhQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Zo7R9QYCQfXHDWY+Brxti7zqbYPSp1ds3jVNB7jZII2ME/xP6Yni/DZl8bduiMuH6yoyHRhx7FgaHb1mQFAvJLMSF1F2mcXsQWW0hG3BQBphx13arzFWB2f+ADBbe3CZ9ls6x33tPB91uHriQ+Sg5zFfSYp31O2koKkvlYkTJzQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=om2RabQW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="om2RabQW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7958FC4CEE7; Sat, 23 Aug 2025 14:32:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755959567; bh=p4K5CW7Fi9zPO5eeTdpL/9ZRiA50DYrX9Hr7mJ8NXhQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=om2RabQW+8k/4Wez1HDxycD62GeMff/qzP0L4EKZE35MLKKIJZBLX/HjQe2yWVDeQ fCF0yf+p7W3HlMNMTo3vCeVLz26QEXFL5aaJengVuY7sY0VL9hY4V4dBkLZUt1RUmM riE1N5D9QxlkOVsYqF0BfGCiKKk/60sHsJKJFVM6kFZrOTTWBnXKXU9R0rGh3SMeJd hOIzeiPNDenil2CgMpNpRZZX6lCbBNQnYcyypg+V5sSTZ92b/9HssRkw2eQBs2rq3I Z+w8fikTVhP1cdD2rXLXjVBeyFNmTYhWdyqueHDlu1etxLNmJgaT6B9lmIYdQ6Tcr6 2E5rakCAqrtsw== From: Sasha Levin To: stable@vger.kernel.org Cc: Bjorn Helgaas , Ulf Hansson , Sasha Levin Subject: [PATCH 6.6.y 1/2] mmc: sdhci-pci-gli: Use PCI AER definitions, not hard-coded values Date: Sat, 23 Aug 2025 10:32:43 -0400 Message-ID: <20250823143244.2247015-1-sashal@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: <2025082238-portal-perfectly-7a53@gregkh> References: <2025082238-portal-perfectly-7a53@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Bjorn Helgaas [ Upstream commit 951b7ccc54591ba48755b5e0c7fc8b9623a64640 ] 015c9cbcf0ad ("mmc: sdhci-pci-gli: GL9750: Mask the replay timer timeout of AER") added PCI_GLI_9750_CORRERR_MASK, the offset of the AER Capability in config space, and PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT, the Replay Timer Timeout bit in the AER Correctable Error Status register. Use pci_find_ext_capability() to locate the AER Capability and use the existing PCI_ERR_COR_REP_TIMER definition to mask the bit. This removes a little bit of unnecessarily device-specific code and makes AER-related things more greppable. Signed-off-by: Bjorn Helgaas Link: https://lore.kernel.org/r/20240327214831.1544595-2-helgaas@kernel.org Signed-off-by: Ulf Hansson Stable-dep-of: dec8b38be4b3 ("mmc: sdhci-pci-gli: Add a new function to simplify the code") Signed-off-by: Sasha Levin --- drivers/mmc/host/sdhci-pci-gli.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c index 11c404374d79..dc6ec90d27f8 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -28,9 +28,6 @@ #define PCI_GLI_9750_PM_CTRL 0xFC #define PCI_GLI_9750_PM_STATE GENMASK(1, 0) -#define PCI_GLI_9750_CORRERR_MASK 0x214 -#define PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT BIT(12) - #define SDHCI_GLI_9750_CFG2 0x848 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) #define GLI_9750_CFG2_L1DLY_VALUE 0x1F @@ -155,9 +152,6 @@ #define PCI_GLI_9755_PM_CTRL 0xFC #define PCI_GLI_9755_PM_STATE GENMASK(1, 0) -#define PCI_GLI_9755_CORRERR_MASK 0x214 -#define PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT BIT(12) - #define SDHCI_GLI_9767_GM_BURST_SIZE 0x510 #define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8) @@ -547,6 +541,7 @@ static void gl9750_hw_setting(struct sdhci_host *host) { struct sdhci_pci_slot *slot = sdhci_priv(host); struct pci_dev *pdev; + int aer; u32 value; pdev = slot->chip->pdev; @@ -568,9 +563,12 @@ static void gl9750_hw_setting(struct sdhci_host *host) pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value); /* mask the replay timer timeout of AER */ - pci_read_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, &value); - value |= PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT; - pci_write_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, value); + aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); + if (aer) { + pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value); + value |= PCI_ERR_COR_REP_TIMER; + pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value); + } gl9750_wt_off(host); } @@ -745,6 +743,7 @@ static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock) static void gl9755_hw_setting(struct sdhci_pci_slot *slot) { struct pci_dev *pdev = slot->chip->pdev; + int aer; u32 value; gl9755_wt_on(pdev); @@ -782,9 +781,12 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot) pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); /* mask the replay timer timeout of AER */ - pci_read_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, &value); - value |= PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT; - pci_write_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, value); + aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); + if (aer) { + pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value); + value |= PCI_ERR_COR_REP_TIMER; + pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value); + } gl9755_wt_off(pdev); } -- 2.50.1