From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3190B1F09A5 for ; Sat, 6 Sep 2025 14:38:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757169509; cv=none; b=Tg/TQBYLKrMS1BYUQ8XZeHkcLeIoxjgsn9d0PzdgieYkGxMym2G1t30k6DZsTK4YZG9oKdz9/PGQHxHcdFmtatD1U5TMzxkfmYap49vNAs7gkeCbUecDDQXGxIHBUfNHRcgkPGWA/veWvnj1CktEXmdI7kAAq3ElT1aVcE2TZD0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757169509; c=relaxed/simple; bh=Tso8u5DXcwLjJkw4rCp9GUUtZGetcd84Y7C8hz7OiPU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oYX6wvDsOyjNS8Zlg/cYEBdo7lxxgSYUXELF+b74J59TbZZFFByUnACNlX3dQdlN6At7CNLDdrAaojDrB79dCKJVr9aQEf7k6qo6rRKV0OrgyYEtcBULDmDP7HWlNXvvhuvmGlRkcWo1OgszCFUQ6n98gtmF6vwOZW46De/14Zc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jULOZ7z2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jULOZ7z2" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 05DFDC4CEE7; Sat, 6 Sep 2025 14:38:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757169508; bh=Tso8u5DXcwLjJkw4rCp9GUUtZGetcd84Y7C8hz7OiPU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jULOZ7z2TCfcbHsg4MBxPHPyKs1sE6gv0c4WCV3ltMzG6gWp/xguu1xMPnMs395GR xkGgVe+HLtYp24ymRZfjkfwIrwootPCGx2zqFU7EJfAGr2FC2qeAaTr7++xXr4iHnj DFDnojLvZAQpm+dnITuqSu8JFVeXY/++/TLvZK1zy8gC9JTnEaSA3a6sLL+RuXDP+M 3E4NEZksOyL21QiHvepOvVUbJmqHv3H5uc7hSj04LoP+2m6fbQe2Es2j7Y835xUlAh KKNHh+cNMml8emR3fqj4KTBIzxHMKitk3nT62UShbt7NyNbVhI/tufj4S5tm/9SjSz y82vBRNGOq9Iw== From: Sasha Levin To: stable@vger.kernel.org Cc: Dapeng Mi , "Peter Zijlstra (Intel)" , Ingo Molnar , Kan Liang , Sasha Levin Subject: [PATCH 6.12.y] perf/x86/intel: Don't clear perf metrics overflow bit unconditionally Date: Sat, 6 Sep 2025 10:38:26 -0400 Message-ID: <20250906143826.44231-1-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <2025042126-outgrow-kiln-e518@gregkh> References: <2025042126-outgrow-kiln-e518@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Dapeng Mi [ Upstream commit a5f5e1238f4ff919816f69e77d2537a48911767b ] The below code would always unconditionally clear other status bits like perf metrics overflow bit once PEBS buffer overflows: status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; This is incorrect. Perf metrics overflow bit should be cleared only when fixed counter 3 in PEBS counter group. Otherwise perf metrics overflow could be missed to handle. Closes: https://lore.kernel.org/all/20250225110012.GK31462@noisy.programming.kicks-ass.net/ Fixes: 7b2c05a15d29 ("perf/x86/intel: Generic support for hardware TopDown metrics") Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Ingo Molnar Reviewed-by: Kan Liang Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20250415104135.318169-1-dapeng1.mi@linux.intel.com Signed-off-by: Sasha Levin --- arch/x86/events/intel/core.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 5e43d390f7a3d..063147d7161b6 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3029,7 +3029,6 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); int bit; int handled = 0; - u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); inc_irq_stat(apic_perf_irqs); @@ -3073,7 +3072,6 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) handled++; x86_pmu_handle_guest_pebs(regs, &data); static_call(x86_pmu_drain_pebs)(regs, &data); - status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; /* * PMI throttle may be triggered, which stops the PEBS event. @@ -3084,6 +3082,15 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) */ if (pebs_enabled != cpuc->pebs_enabled) wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); + + /* + * Above PEBS handler (PEBS counters snapshotting) has updated fixed + * counter 3 and perf metrics counts if they are in counter group, + * unnecessary to update again. + */ + if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] && + is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS])) + status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT; } /* @@ -3103,6 +3110,8 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) static_call(intel_pmu_update_topdown_event)(NULL); } + status &= hybrid(cpuc->pmu, intel_ctrl); + /* * Checkpointed counters can lead to 'spurious' PMIs because the * rollback caused by the PMI will have cleared the overflow status -- 2.51.0