From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7523410E0 for ; Sat, 6 Sep 2025 19:48:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757188105; cv=none; b=WkM0rKAbHVCqt9FW65J/s7uRIiNPo6IwDeYo+7NCZF4n7WnTbd4CfBeF+u+PCHJGK7pb0Bem7xf0ztXvN3TjyNKdPI8NPSetx/3IDobFfi2jhvuPWeGjXquVzCZqmaSFnumv97ysKfcHfYdUxYLyd1/kuwGfp93XNHC7BdemgO8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757188105; c=relaxed/simple; bh=wdGUaf0MHi/tIKEPW5DSQBWzNUeQahvH4o6s3cyKkbI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lGQWw/BsA8S20QgFx5tmy5axD5wO4Im+NdC7f5CQ9Pnb8N87zLtZlEVTMiXdTZIMQh+5IG8pAMzzgXaEkFHFO1FC0k9qpbC5B8db/2C4h6Looq6ec/i269PfdaMRICjd/l+P775yYJczwHXGLZnKxuC/uA4zBWi11Y1GpjEY09c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AiEKoXYb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AiEKoXYb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 52963C4CEE7; Sat, 6 Sep 2025 19:48:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757188105; bh=wdGUaf0MHi/tIKEPW5DSQBWzNUeQahvH4o6s3cyKkbI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AiEKoXYb0vqcyA9i/FW9QUqkGLYlUhQJXPW+7CSthKH3RdIJ19gdvtynVBkfAjhGl bxGTMGRin4wVrjvQV1gYCTFjJWLq/A8vqdA6r1pMHT7exHdIauiyoCbnEzGhBBW7vj 0UqZPILRg//aSqUqFCaZHUxZ7Jn34rOpKqPSvaKJf30L5f/Kta1deJmVONV2Sy5xLP dvfGecUfbJSAg6ByAYRyGiLHBBDjwvZroo/Sn6xTWpR2p4hWEaXevWRCohq7viRvnx kx2ngH+jTIhMyJxMWTobGk9y2wfeSIYdbTi1N76bsGKPYnnVY2Ltb8bCjkJsCV8v73 Y8VYQFy8qERgw== From: Sasha Levin To: stable@vger.kernel.org Cc: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , AngeloGioacchino Del Regno , Daniel Lezcano , Sasha Levin Subject: [PATCH 6.12.y] thermal/drivers/mediatek/lvts: Disable low offset IRQ for minimum threshold Date: Sat, 6 Sep 2025 15:48:21 -0400 Message-ID: <20250906194821.208326-1-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <2025041731-qualifier-football-8dbd@gregkh> References: <2025041731-qualifier-football-8dbd@gregkh> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Nícolas F. R. A. Prado [ Upstream commit fa17ff8e325a657c84be1083f06e54ee7eea82e4 ] In order to get working interrupts, a low offset value needs to be configured. The minimum value for it is 20 Celsius, which is what is configured when there's no lower thermal trip (ie the thermal core passes -INT_MAX as low trip temperature). However, when the temperature gets that low and fluctuates around that value it causes an interrupt storm. Prevent that interrupt storm by not enabling the low offset interrupt if the low threshold is the minimum one. Cc: stable@vger.kernel.org Fixes: 77354eaef821 ("thermal/drivers/mediatek/lvts_thermal: Don't leave threshold zeroed") Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20250113-mt8192-lvts-filtered-suspend-fix-v2-3-07a25200c7c6@collabora.com Signed-off-by: Daniel Lezcano [ Adapted interrupt mask definitions ] Signed-off-by: Sasha Levin --- drivers/thermal/mediatek/lvts_thermal.c | 50 ++++++++++++++++++------- 1 file changed, 36 insertions(+), 14 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c index 017191b9f8645..e6fe6cc35821d 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -66,10 +66,14 @@ #define LVTS_TSSEL_CONF 0x13121110 #define LVTS_CALSCALE_CONF 0x300 -#define LVTS_MONINT_OFFSET_SENSOR0 0xC -#define LVTS_MONINT_OFFSET_SENSOR1 0x180 -#define LVTS_MONINT_OFFSET_SENSOR2 0x3000 -#define LVTS_MONINT_OFFSET_SENSOR3 0x3000000 +#define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR0 BIT(3) +#define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR1 BIT(8) +#define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR2 BIT(13) +#define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR3 BIT(25) +#define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR0 BIT(2) +#define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR1 BIT(7) +#define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR2 BIT(12) +#define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR3 BIT(24) #define LVTS_INT_SENSOR0 0x0009001F #define LVTS_INT_SENSOR1 0x001203E0 @@ -329,23 +333,41 @@ static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl) { - u32 masks[] = { - LVTS_MONINT_OFFSET_SENSOR0, - LVTS_MONINT_OFFSET_SENSOR1, - LVTS_MONINT_OFFSET_SENSOR2, - LVTS_MONINT_OFFSET_SENSOR3, + static const u32 high_offset_inten_masks[] = { + LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR0, + LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR1, + LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR2, + LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR3, + }; + static const u32 low_offset_inten_masks[] = { + LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR0, + LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR1, + LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR2, + LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR3, }; u32 value = 0; int i; value = readl(LVTS_MONINT(lvts_ctrl->base)); - for (i = 0; i < ARRAY_SIZE(masks); i++) { + for (i = 0; i < ARRAY_SIZE(high_offset_inten_masks); i++) { if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh - && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) - value |= masks[i]; - else - value &= ~masks[i]; + && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) { + /* + * The minimum threshold needs to be configured in the + * OFFSETL register to get working interrupts, but we + * don't actually want to generate interrupts when + * crossing it. + */ + if (lvts_ctrl->low_thresh == -INT_MAX) { + value &= ~low_offset_inten_masks[i]; + value |= high_offset_inten_masks[i]; + } else { + value |= low_offset_inten_masks[i] | high_offset_inten_masks[i]; + } + } else { + value &= ~(low_offset_inten_masks[i] | high_offset_inten_masks[i]); + } } writel(value, LVTS_MONINT(lvts_ctrl->base)); -- 2.51.0