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Mon, 22 Sep 2025 06:02:21 -0700 (PDT) Received: from ziepe.ca ([130.41.10.202]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-269802deb3dsm132892235ad.93.2025.09.22.06.02.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Sep 2025 06:02:20 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1v0gBP-0000000ALNw-0bkc; Mon, 22 Sep 2025 10:02:19 -0300 Date: Mon, 22 Sep 2025 10:02:19 -0300 From: Jason Gunthorpe To: Vasant Hegde Cc: iommu@lists.linux.dev, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, suravee.suthikulpanit@amd.com, Alejandro Jimenez , stable@vger.kernel.org, Joao Martins Subject: Re: [PATCH] iommu/amd/pgtbl: Fix possible race while increase page table level Message-ID: <20250922130219.GX1326709@ziepe.ca> References: <20250911121416.633216-1-vasant.hegde@amd.com> <20250918141737.GP1326709@ziepe.ca> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Mon, Sep 22, 2025 at 03:35:07PM +0530, Vasant Hegde wrote: > > IMHO unless someone is actually hitting this I'd leave it and focus on > > merging iomupt which fully fixes this without adding any locks to the > > fast path. > > Unfortunately yes. We had customer reporting this issue. If a customer is actually hitting this then you definately need to solve the whole problem including the mmap race. I guess adding a lock makes it easer to deal with, but this: + write_seqcount_begin(&pgtable->seqcount); pgtable->root = pte; pgtable->mode += 1; + write_seqcount_end(&pgtable->seqcount); + amd_iommu_update_and_flush_device_table(domain); Is out of order. The DTE has to be updated and caches flushed *before* writing the new information to the pgtable for other threads to observe. You can look at what I did, but broadly you have to feed the new top as a function argument through to set_dte: static void set_dte_entry(struct amd_iommu *iommu, - struct iommu_dev_data *dev_data) + struct iommu_dev_data *dev_data, + phys_addr_t top_paddr, unsigned int top_level) { u16 domid; So the above can be ordered correctly. You may also want to think about just disabling this optimization, always start with a 6 level table. Jason