From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48C72330B3A; Fri, 17 Oct 2025 15:44:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760715846; cv=none; b=LY3Cgt+XyjfNmh8qw98zsuzNB97s6DUA8vleihQ3wpSuOrj/1+/DBeO7zxp+Qjf4ydWkOanPJpUxTr2Vehb68wFcrmHsbw/OhYKfSM3N0zuM6GwI5SzhV+u/BbrznMxb5jzbnCq7l0QKyByFj1COUdzA1EqpxfbdP5jryIzhtso= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760715846; c=relaxed/simple; bh=ugJV6zFScW+SJJetd5EjTISELp5gmMJRBoDCJwS8BRg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PM1Vc4+pgPszDQXW5RMhKXoGEQoL6diUQKSp3ZscxX7BJOUgasbt03eyZuCIYTLyfbxTnYJzPj+ucOyIOL4NhDb/t8LUaVlDtlZFBiyrAUwS7tIJHrxyAEhnLg2Nb4S24EBjhfUJ69oiECYxdwHmgaDrDUA5faRMOzYAZPMUQgQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=UbsKz/ES; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="UbsKz/ES" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C7FBCC113D0; Fri, 17 Oct 2025 15:44:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1760715846; bh=ugJV6zFScW+SJJetd5EjTISELp5gmMJRBoDCJwS8BRg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UbsKz/ESqe/F3tzTDiNGzQZqFmnbEeKrNNQ4T+xCz231bw5ZXDuSHdhi5sExQaTmH TES85SZkyjGVN45nSpXLaNP7eVelH0FNpufRMKjFkJJBQEH6ioHu7go8pabCd4sBly Jgr8Aq5IqarhSnGylj7g8yQtKI1YQiN6F59RMQa4= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Jia Wang , Charles Mirabile , Lucas Zampieri , Thomas Gleixner , Sasha Levin Subject: [PATCH 6.17 358/371] irqchip/sifive-plic: Avoid interrupt ID 0 handling during suspend/resume Date: Fri, 17 Oct 2025 16:55:33 +0200 Message-ID: <20251017145215.041008613@linuxfoundation.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251017145201.780251198@linuxfoundation.org> References: <20251017145201.780251198@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.17-stable review patch. If anyone has any objections, please let me know. ------------------ From: Lucas Zampieri [ Upstream commit f75e07bf5226da640fa99a0594687c780d9bace4 ] According to the PLIC specification[1], global interrupt sources are assigned small unsigned integer identifiers beginning at the value 1. An interrupt ID of 0 is reserved to mean "no interrupt". The current plic_irq_resume() and plic_irq_suspend() functions incorrectly start the loop from index 0, which accesses the register space for the reserved interrupt ID 0. Change the loop to start from index 1, skipping the reserved interrupt ID 0 as per the PLIC specification. This prevents potential undefined behavior when accessing the reserved register space during suspend/resume cycles. Fixes: e80f0b6a2cf3 ("irqchip/irq-sifive-plic: Add syscore callbacks for hibernation") Co-developed-by: Jia Wang Signed-off-by: Jia Wang Co-developed-by: Charles Mirabile Signed-off-by: Charles Mirabile Signed-off-by: Lucas Zampieri Signed-off-by: Thomas Gleixner Link: https://github.com/riscv/riscv-plic-spec/releases/tag/1.0.0 Signed-off-by: Sasha Levin --- drivers/irqchip/irq-sifive-plic.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index bf69a4802b71e..9c4af7d588463 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -252,7 +252,8 @@ static int plic_irq_suspend(void) priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; - for (i = 0; i < priv->nr_irqs; i++) { + /* irq ID 0 is reserved */ + for (i = 1; i < priv->nr_irqs; i++) { __assign_bit(i, priv->prio_save, readl(priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID)); } @@ -283,7 +284,8 @@ static void plic_irq_resume(void) priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; - for (i = 0; i < priv->nr_irqs; i++) { + /* irq ID 0 is reserved */ + for (i = 1; i < priv->nr_irqs; i++) { index = BIT_WORD(i); writel((priv->prio_save[index] & BIT_MASK(i)) ? 1 : 0, priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID); -- 2.51.0