From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 524BA1A00CE for ; Sat, 18 Oct 2025 02:05:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760753120; cv=none; b=pwh4wiEnVgYx4BUZ6MtWCgmvm3W1OFWOfV2deTlvQTepIVeuxw8YonLszqY2cnVWAf3uT4KvZrQxib6HWXxtVDSmWE5oo7XTwj4OraN3ZM+b0ZvLbrcrWT9wD6xo2PHAXlkRLF9sBLRIU4kOsg4ptKCB7nq2EUnddWTH7Mjw8qM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760753120; c=relaxed/simple; bh=vOP7rzSbDBaPqYc1/3aodI/G4XOW4eVUJAdUjr/KUTI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GjCZgCuVj6h4n6gGkIvE/CcoZIxUhjgtcj8qqWZgUzjb1S/1eGC6oAuh2COZNbl8NECMP15T3VnClvSoortAOTJ72SRpG9FigK47eya7Ukv6RtgSxofAZSA0tDAtqQh2qsrmkTGP1GHg7Ae+cBg8OD+D1LR3rqbnNN5Kv0A2KJA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=omK875jJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="omK875jJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 60F01C4CEFE; Sat, 18 Oct 2025 02:05:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760753119; bh=vOP7rzSbDBaPqYc1/3aodI/G4XOW4eVUJAdUjr/KUTI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=omK875jJLxgxNPuk1OIwBnyU7i66HySfJGB9iFhWPNRGrrxyvz2qvs3AnpOtPcvuj N2ahzEMW1be4TJFSiB2wCYAIW7CRiDfezFMHA+f1giDyyjZzeaKtpIhxJA5xXamWOE akLdxpf2J5JtAKyRub8AheqmMTll+m6PiT9lEyE7/fOolHXBqri9Z+0ltzovwDUZjr xMaS9mrXrfSic+f5l7nWv5/n6wM4JaEuUks0llEBK+71h3CSyaouTMEwPP0kCcU8JR vMjDY/UeS6lG3bhSUnvGhKUM/bYuTGEnxAZ1ApKn/BsMt5aUwvdLGIbp0GgxLw4A13 xSwZYz3khhrRg== From: Sasha Levin To: stable@vger.kernel.org Cc: Kaustabh Chakraborty , Inki Dae , Sasha Levin Subject: [PATCH 6.12.y 2/3] drm/exynos: exynos7_drm_decon: properly clear channels during bind Date: Fri, 17 Oct 2025 22:05:14 -0400 Message-ID: <20251018020515.208843-2-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251018020515.208843-1-sashal@kernel.org> References: <2025101639-survey-affix-387d@gregkh> <20251018020515.208843-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Kaustabh Chakraborty [ Upstream commit 5f1a453974204175f20b3788824a0fe23cc36f79 ] The DECON channels are not cleared properly as the windows aren't shadow protected. When accompanied with an IOMMU, it pagefaults, and the kernel panics. Implement shadow protect/unprotect, along with a standalone update, for channel clearing to properly take effect. Signed-off-by: Kaustabh Chakraborty Signed-off-by: Inki Dae Stable-dep-of: e1361a4f1be9 ("drm/exynos: exynos7_drm_decon: remove ctx->suspended") Signed-off-by: Sasha Levin --- drivers/gpu/drm/exynos/exynos7_drm_decon.c | 55 +++++++++++++--------- 1 file changed, 32 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c index 99cc3f6803c7a..2cc2962d4ef3a 100644 --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c @@ -81,6 +81,28 @@ static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { DRM_PLANE_TYPE_CURSOR, }; +/** + * decon_shadow_protect_win() - disable updating values from shadow registers at vsync + * + * @ctx: display and enhancement controller context + * @win: window to protect registers for + * @protect: 1 to protect (disable updates) + */ +static void decon_shadow_protect_win(struct decon_context *ctx, + unsigned int win, bool protect) +{ + u32 bits, val; + + bits = SHADOWCON_WINx_PROTECT(win); + + val = readl(ctx->regs + SHADOWCON); + if (protect) + val |= bits; + else + val &= ~bits; + writel(val, ctx->regs + SHADOWCON); +} + static void decon_wait_for_vblank(struct decon_context *ctx) { if (ctx->suspended) @@ -101,18 +123,27 @@ static void decon_wait_for_vblank(struct decon_context *ctx) static void decon_clear_channels(struct decon_context *ctx) { unsigned int win, ch_enabled = 0; + u32 val; /* Check if any channel is enabled. */ for (win = 0; win < WINDOWS_NR; win++) { - u32 val = readl(ctx->regs + WINCON(win)); + val = readl(ctx->regs + WINCON(win)); if (val & WINCONx_ENWIN) { + decon_shadow_protect_win(ctx, win, true); + val &= ~WINCONx_ENWIN; writel(val, ctx->regs + WINCON(win)); ch_enabled = 1; + + decon_shadow_protect_win(ctx, win, false); } } + val = readl(ctx->regs + DECON_UPDATE); + val |= DECON_UPDATE_STANDALONE_F; + writel(val, ctx->regs + DECON_UPDATE); + /* Wait for vsync, as disable channel takes effect at next vsync */ if (ch_enabled) decon_wait_for_vblank(ctx); @@ -340,28 +371,6 @@ static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win) writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); } -/** - * decon_shadow_protect_win() - disable updating values from shadow registers at vsync - * - * @ctx: display and enhancement controller context - * @win: window to protect registers for - * @protect: 1 to protect (disable updates) - */ -static void decon_shadow_protect_win(struct decon_context *ctx, - unsigned int win, bool protect) -{ - u32 bits, val; - - bits = SHADOWCON_WINx_PROTECT(win); - - val = readl(ctx->regs + SHADOWCON); - if (protect) - val |= bits; - else - val &= ~bits; - writel(val, ctx->regs + SHADOWCON); -} - static void decon_atomic_begin(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = crtc->ctx; -- 2.51.0