From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15E1A1F5821 for ; Sat, 18 Oct 2025 02:26:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760754406; cv=none; b=IMJzOrJM3qzpgXrUhPjLPwo8oc8bNDIxI85x6gHPINeNFEBg44a2RjF8wh3eH2vetB8sIu4M6zM4o60MXVafdw5d1j7llG0BqY5C7QDjzbbhtsoUIkGLM5WHZLbuiYp8JzsEE9NlijqvSogjcDhM+9pw96GHtmGcRcS/XRSrAg8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760754406; c=relaxed/simple; bh=Zq1Swjq8uNdzQu/1z7wxXGKOMFQnoFBI1ldRYP08rIk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ofw4Ldq6BGRMnNrKueJLIKUO2xjDp8PqoTIU6aNkDbZLA2qnCdVdMoes0u/EaBphz/pkHk/S2UVuQzqPxE1y74UaUHFJDpp9o5wiftMO5+eHVoOWVkRz9TN8k5FF5kCZz9R3f9eXegzvffobXxNw3wHj3FgU+C8z4OZqdPMkr3k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JJj6Snqt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JJj6Snqt" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 605EBC4CEFE; Sat, 18 Oct 2025 02:26:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760754405; bh=Zq1Swjq8uNdzQu/1z7wxXGKOMFQnoFBI1ldRYP08rIk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JJj6SnqtKQKi1HdUrUEhlY+3pX1EK/W6jRWYfCkXFpRe+V9tPfG9RPrtbAGx2Cytj /87zTmBEC7Jyc52Izvs9d6ASoTALo9KAhFPXc46rUuHFitQr4gChWugr7MqH3/cl06 tsCm7Ew4q2VCTvEJcb/IhrXP+X/VWRQjOBjDHUBgllj79mKmPUTvbmG9kiY4qdnB4s QaHQzjGhpykOgJG1K1Z/ZiwiWk5oFsOiiwqME4ZnafHwq0iN7TUaNMUVC3zFKBJEyi CT0eMW8kRZLzNiiEo1V+WeLp8pyEGoTzDqOSSPGo/rWwdx2yWgWy6qASfkXaQoIymJ vqB9AfJl/Te9w== From: Sasha Levin To: stable@vger.kernel.org Cc: Kaustabh Chakraborty , Inki Dae , Sasha Levin Subject: [PATCH 6.1.y 2/3] drm/exynos: exynos7_drm_decon: properly clear channels during bind Date: Fri, 17 Oct 2025 22:26:41 -0400 Message-ID: <20251018022642.218123-2-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251018022642.218123-1-sashal@kernel.org> References: <2025101640-sprig-fifth-f5a1@gregkh> <20251018022642.218123-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Kaustabh Chakraborty [ Upstream commit 5f1a453974204175f20b3788824a0fe23cc36f79 ] The DECON channels are not cleared properly as the windows aren't shadow protected. When accompanied with an IOMMU, it pagefaults, and the kernel panics. Implement shadow protect/unprotect, along with a standalone update, for channel clearing to properly take effect. Signed-off-by: Kaustabh Chakraborty Signed-off-by: Inki Dae Stable-dep-of: e1361a4f1be9 ("drm/exynos: exynos7_drm_decon: remove ctx->suspended") Signed-off-by: Sasha Levin --- drivers/gpu/drm/exynos/exynos7_drm_decon.c | 55 +++++++++++++--------- 1 file changed, 32 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c index 6d18a20e1104d..6223c89a66548 100644 --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c @@ -82,6 +82,28 @@ static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { DRM_PLANE_TYPE_CURSOR, }; +/** + * decon_shadow_protect_win() - disable updating values from shadow registers at vsync + * + * @ctx: display and enhancement controller context + * @win: window to protect registers for + * @protect: 1 to protect (disable updates) + */ +static void decon_shadow_protect_win(struct decon_context *ctx, + unsigned int win, bool protect) +{ + u32 bits, val; + + bits = SHADOWCON_WINx_PROTECT(win); + + val = readl(ctx->regs + SHADOWCON); + if (protect) + val |= bits; + else + val &= ~bits; + writel(val, ctx->regs + SHADOWCON); +} + static void decon_wait_for_vblank(struct decon_context *ctx) { if (ctx->suspended) @@ -102,18 +124,27 @@ static void decon_wait_for_vblank(struct decon_context *ctx) static void decon_clear_channels(struct decon_context *ctx) { unsigned int win, ch_enabled = 0; + u32 val; /* Check if any channel is enabled. */ for (win = 0; win < WINDOWS_NR; win++) { - u32 val = readl(ctx->regs + WINCON(win)); + val = readl(ctx->regs + WINCON(win)); if (val & WINCONx_ENWIN) { + decon_shadow_protect_win(ctx, win, true); + val &= ~WINCONx_ENWIN; writel(val, ctx->regs + WINCON(win)); ch_enabled = 1; + + decon_shadow_protect_win(ctx, win, false); } } + val = readl(ctx->regs + DECON_UPDATE); + val |= DECON_UPDATE_STANDALONE_F; + writel(val, ctx->regs + DECON_UPDATE); + /* Wait for vsync, as disable channel takes effect at next vsync */ if (ch_enabled) decon_wait_for_vblank(ctx); @@ -341,28 +372,6 @@ static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win) writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); } -/** - * decon_shadow_protect_win() - disable updating values from shadow registers at vsync - * - * @ctx: display and enhancement controller context - * @win: window to protect registers for - * @protect: 1 to protect (disable updates) - */ -static void decon_shadow_protect_win(struct decon_context *ctx, - unsigned int win, bool protect) -{ - u32 bits, val; - - bits = SHADOWCON_WINx_PROTECT(win); - - val = readl(ctx->regs + SHADOWCON); - if (protect) - val |= bits; - else - val &= ~bits; - writel(val, ctx->regs + SHADOWCON); -} - static void decon_atomic_begin(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = crtc->ctx; -- 2.51.0