From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E35F22F5A1B for ; Mon, 27 Oct 2025 13:49:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761572975; cv=none; b=Gp/qdjdga+7diu7a7lIj7nSdSzdIbOXbAzxWukOz02ZCCq/sPkwk4mtkBgdw/MEjVLkayhOX05olz3jzldK+naWJJ2EYrkqTZau340Ib1469Sq+Xl2ulU10/R4Lc+2k/74IXw9vReJedRbOH48Wu9pDxBS+lRTpOuhdqMLaNXTA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761572975; c=relaxed/simple; bh=XDbkV+H0yI4wexyYq4NG8JY2zCbOz5PXohZeK4pjvFo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tlloBvhqREW2dH8uoFOYxkhZHLU93pBSImicCEpYQrvlKfkGo3N0MTnSYhSuc48Pbk90/LPtmHU8aoIXxRHwfUHntbEqE+pZIOAy5z2IupA3efn+hOK7HnhlYhtBHtCZhHsLS6qOL8mciYMzkU8NGivkBzfiK+RJLHsrDvei4rA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TZdhk8lH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TZdhk8lH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CA623C116B1; Mon, 27 Oct 2025 13:49:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761572974; bh=XDbkV+H0yI4wexyYq4NG8JY2zCbOz5PXohZeK4pjvFo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TZdhk8lHka0BDuizQCgRztb6H8Lg6UvYUqgdOMKfHqDfTcBBTVAOBu3Dz/dXATXbi ZNwPmWnKZcCX64SlSgICcCkeU6E7CJpaENbYTHeIfhWwwgWx7B1FtW3KZwvpiwqKFo LvAZuMSKmRtXGgrdcxNo+pheG1Q64abNbUcRMR75MTIix7d9TpQ15MlijNBFN0XVZX ujRX8Fpgl9SItEWTzQOEFMPb9NFdHOTZmAwIyqnknJWPycYWpk6wzonv+MIx074VWG XWG6i45o0EX2EZjwSzgY/3gmKKIdCal8cUKRZhclD53Sq+2Ypvtarzcg4AAKGdBUu5 Klyr+EKbGjWiA== From: Sasha Levin To: stable@vger.kernel.org Cc: Lad Prabhakar , Fabrizio Castro , =?UTF-8?q?Niklas=20S=C3=B6derlund?= , Jakub Kicinski , Sasha Levin Subject: [PATCH 5.15.y 2/2] net: ravb: Enforce descriptor type ordering Date: Mon, 27 Oct 2025 09:49:31 -0400 Message-ID: <20251027134931.492032-2-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251027134931.492032-1-sashal@kernel.org> References: <2025102623-footless-outcast-b793@gregkh> <20251027134931.492032-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Lad Prabhakar [ Upstream commit 5370c31e84b0e0999c7b5ff949f4e104def35584 ] Ensure the TX descriptor type fields are published in a safe order so the DMA engine never begins processing a descriptor chain before all descriptor fields are fully initialised. For multi-descriptor transmits the driver writes DT_FEND into the last descriptor and DT_FSTART into the first. The DMA engine begins processing when it observes DT_FSTART. Move the dma_wmb() barrier so it executes immediately after DT_FEND and immediately before writing DT_FSTART (and before DT_FSINGLE in the single-descriptor case). This guarantees that all prior CPU writes to the descriptor memory are visible to the device before DT_FSTART is seen. This avoids a situation where compiler/CPU reordering could publish DT_FSTART ahead of DT_FEND or other descriptor fields, allowing the DMA to start on a partially initialised chain and causing corrupted transmissions or TX timeouts. Such a failure was observed on RZ/G2L with an RT kernel as transmit queue timeouts and device resets. Fixes: 2f45d1902acf ("ravb: minimize TX data copying") Cc: stable@vger.kernel.org Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar Reviewed-by: Niklas Söderlund Link: https://patch.msgid.link/20251017151830.171062-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/renesas/ravb_main.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index ad61226098973..5ceab1457108f 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1668,13 +1668,25 @@ static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) skb_tx_timestamp(skb); } - /* Descriptor type must be set after all the above writes */ - dma_wmb(); + if (num_tx_desc > 1) { desc->die_dt = DT_FEND; desc--; + /* When using multi-descriptors, DT_FEND needs to get written + * before DT_FSTART, but the compiler may reorder the memory + * writes in an attempt to optimize the code. + * Use a dma_wmb() barrier to make sure DT_FEND and DT_FSTART + * are written exactly in the order shown in the code. + * This is particularly important for cases where the DMA engine + * is already running when we are running this code. If the DMA + * sees DT_FSTART without the corresponding DT_FEND it will enter + * an error condition. + */ + dma_wmb(); desc->die_dt = DT_FSTART; } else { + /* Descriptor type must be set after all the above writes */ + dma_wmb(); desc->die_dt = DT_FSINGLE; } ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); -- 2.51.0